03-11-2015, 02:30 PM
(This post was last modified: 03-14-2015, 04:56 AM by LordDecapo.)
So as many of you know I have been working on my IizR IS and Architecture for quite some time now. I have learned so much on this journey to making a system I can be truly proud of.
On this journey I have gotten assistance with many aspects of the system and in that process met a bunch of great people (love you ppl of ORE! And I thank you... Special shout out to Dylan and Voltz who have been helping me since nearly the beginning and continue to do so)
Also thanks Embi for the bad ass 6tick ALU design
that along with a bussing issue (couldn't export the PCs current value via parellel bus to an external program memory) is why I went from IizR13 to 14.
So now I finally feel I need to commit to a system and finish it to fully run all the programs and features we have been adding and planning over all this time.
I know I have said this before, yet this time I mean it. I truly can not find an honest benifit from increasing the clock speed any farther or changing the stages. As they have been refined so much; changing it would end up speeding up one thing and slowing down another. Any changes to that would have to happen after being able to fully test the programs we plan to make. So as of now the following will be accurate and only subject to very minor changes (if a bug comes up)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The final Specs are as follows;
-6 Tick Clock (1.667hz)
-6 Stage pipeline (3 of which are just fetching from my massive PROM, so the CPU itself is only 4)
-both software and hardware based Interrupts
-256 Bytes of RAM (31 are memory mapped to PC, stack over flow, system status etc) (6 cycle access penalty)
-16 Bytes of LRU-2 L1 Cache (2 cycle access penalty)
-32 Bytes of LRU L2 Cache (4 cycle access penalty)
-14 GPR's (some of which will be kernel/function specific, will define in detail at later date)
-15th register is mapped to a data stack
-there is a ZR
-256 Bytes of PROM (will hold a VERY VERY basic kernel as well as a bunch of predefined functions)
-Dual 8bit PCs, to allow you to access apx 16k lines of code from an external source
-Timer (for various uses)
-and of course it features the IizR-IS and uses IizR Architecture (both are my brain child babies, and I love them both with all my heart haha)
~~~
These specs are an improvement over the 8 Stage 10 tick clock IizR12 design and the 6 Stage 8 tick clock IizR13.
NOTE: IizR14 has 1 stage more then IizR13, but the CPU it self is still the same 4 stages, the extra stage had to be added so I can still access 256 Byte PROM.
_______
I am currently at work so it's hard to add pictures, but later today I will upload a picture of the newest IS and a recent shot of the CPU progress.
Also there will be documentation released closer to completion that will explain my architecture and system as well as instructions on how to use and program it that should be HIGHLY indepth.
TL;DR IizR14 is better then IizR13, and made it since I got a faster ALU, and had a major bussing bug I overlooked.
Thanks for reading
On this journey I have gotten assistance with many aspects of the system and in that process met a bunch of great people (love you ppl of ORE! And I thank you... Special shout out to Dylan and Voltz who have been helping me since nearly the beginning and continue to do so)
Also thanks Embi for the bad ass 6tick ALU design
that along with a bussing issue (couldn't export the PCs current value via parellel bus to an external program memory) is why I went from IizR13 to 14.
So now I finally feel I need to commit to a system and finish it to fully run all the programs and features we have been adding and planning over all this time.
I know I have said this before, yet this time I mean it. I truly can not find an honest benifit from increasing the clock speed any farther or changing the stages. As they have been refined so much; changing it would end up speeding up one thing and slowing down another. Any changes to that would have to happen after being able to fully test the programs we plan to make. So as of now the following will be accurate and only subject to very minor changes (if a bug comes up)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The final Specs are as follows;
-6 Tick Clock (1.667hz)
-6 Stage pipeline (3 of which are just fetching from my massive PROM, so the CPU itself is only 4)
-both software and hardware based Interrupts
-256 Bytes of RAM (31 are memory mapped to PC, stack over flow, system status etc) (6 cycle access penalty)
-16 Bytes of LRU-2 L1 Cache (2 cycle access penalty)
-32 Bytes of LRU L2 Cache (4 cycle access penalty)
-14 GPR's (some of which will be kernel/function specific, will define in detail at later date)
-15th register is mapped to a data stack
-there is a ZR
-256 Bytes of PROM (will hold a VERY VERY basic kernel as well as a bunch of predefined functions)
-Dual 8bit PCs, to allow you to access apx 16k lines of code from an external source
-Timer (for various uses)
-and of course it features the IizR-IS and uses IizR Architecture (both are my brain child babies, and I love them both with all my heart haha)
~~~
These specs are an improvement over the 8 Stage 10 tick clock IizR12 design and the 6 Stage 8 tick clock IizR13.
NOTE: IizR14 has 1 stage more then IizR13, but the CPU it self is still the same 4 stages, the extra stage had to be added so I can still access 256 Byte PROM.
_______
I am currently at work so it's hard to add pictures, but later today I will upload a picture of the newest IS and a recent shot of the CPU progress.
Also there will be documentation released closer to completion that will explain my architecture and system as well as instructions on how to use and program it that should be HIGHLY indepth.
TL;DR IizR14 is better then IizR13, and made it since I got a faster ALU, and had a major bussing bug I overlooked.
Thanks for reading
![[Image: ASg6E0U.png]](http://i.imgur.com/ASg6E0U.png)