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+---- Thread: IizR14 (/thread-5960.html)
IizR14 - LordDecapo - 03-11-2015
So as many of you know I have been working on my IizR IS and Architecture for quite some time now. I have learned so much on this journey to making a system I can be truly proud of.
On this journey I have gotten assistance with many aspects of the system and in that process met a bunch of great people (love you ppl of ORE! And I thank you... Special shout out to Dylan and Voltz who have been helping me since nearly the beginning and continue to do so)
Also thanks Embi for the bad ass 6tick ALU design
that along with a bussing issue (couldn't export the PCs current value via parellel bus to an external program memory) is why I went from IizR13 to 14.
So now I finally feel I need to commit to a system and finish it to fully run all the programs and features we have been adding and planning over all this time.
I know I have said this before, yet this time I mean it. I truly can not find an honest benifit from increasing the clock speed any farther or changing the stages. As they have been refined so much; changing it would end up speeding up one thing and slowing down another. Any changes to that would have to happen after being able to fully test the programs we plan to make. So as of now the following will be accurate and only subject to very minor changes (if a bug comes up)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
The final Specs are as follows;
-6 Tick Clock (1.667hz)
-6 Stage pipeline (3 of which are just fetching from my massive PROM, so the CPU itself is only 4)
-both software and hardware based Interrupts
-256 Bytes of RAM (31 are memory mapped to PC, stack over flow, system status etc) (6 cycle access penalty)
-16 Bytes of LRU-2 L1 Cache (2 cycle access penalty)
-32 Bytes of LRU L2 Cache (4 cycle access penalty)
-14 GPR's (some of which will be kernel/function specific, will define in detail at later date)
-15th register is mapped to a data stack
-there is a ZR
-256 Bytes of PROM (will hold a VERY VERY basic kernel as well as a bunch of predefined functions)
-Dual 8bit PCs, to allow you to access apx 16k lines of code from an external source
-Timer (for various uses)
-and of course it features the IizR-IS and uses IizR Architecture (both are my brain child babies, and I love them both with all my heart haha)
~~~
These specs are an improvement over the 8 Stage 10 tick clock IizR12 design and the 6 Stage 8 tick clock IizR13.
NOTE: IizR14 has 1 stage more then IizR13, but the CPU it self is still the same 4 stages, the extra stage had to be added so I can still access 256 Byte PROM.
_______
I am currently at work so it's hard to add pictures, but later today I will upload a picture of the newest IS and a recent shot of the CPU progress.
Also there will be documentation released closer to completion that will explain my architecture and system as well as instructions on how to use and program it that should be HIGHLY indepth.
TL;DR IizR14 is better then IizR13, and made it since I got a faster ALU, and had a major bussing bug I overlooked.
Thanks for reading
RE: IizR14 - VoltzLive - 03-11-2015
happy to help on such an amazing project.
RE: IizR14 - LordDecapo - 03-11-2015
(03-11-2015, 03:30 PM)VoltzLive Wrote: happy to help on such an amazing project.
been great having someone to criticize my ideas from more of a software perspective.I think we have found a happy median between hardware and software opimization
RE: IizR14 - greatgamer34 - 03-11-2015
Im looking forward to this!
I love the 2 levels of caching. I hope you actually get r done this time :3
RE: IizR14 - fuirippu - 03-11-2015
Can't wait to see this implemented... hopefully I'll have time to study the IS and have a program ready to run (...or ready to debug at least)
(03-11-2015, 02:30 PM)LordDecapo Wrote: -there is a ZR
What's a ZR ?
Quote: -256 Bytes of PROM (will hold a VERY VERY basic kernel as well as a bunch of predefined functions)
-Dual 8bit PCs, to allow you to access apx 16k lines of code from an external source
Does this mean that the PROM is purely for the CPU, and that "user code" is supplied from the external source?
RE: IizR14 - LordDecapo - 03-12-2015
(03-11-2015, 08:56 PM)fuirippu Wrote: Can't wait to see this implemented... hopefully I'll have time to study the IS and have a program ready to run (...or ready to debug at least)
(03-11-2015, 02:30 PM)LordDecapo Wrote: -there is a ZR
What's a ZR ?
Quote: -256 Bytes of PROM (will hold a VERY VERY basic kernel as well as a bunch of predefined functions)
-Dual 8bit PCs, to allow you to access apx 16k lines of code from an external source
Does this mean that the PROM is purely for the CPU, and that "user code" is supplied from the external source?
ZR = Zero Register
only for the copies of the CPU that will have the kernel, if you want to just run a single small program that is fully self contained u can load that no problem into the PROM, i said that part cause in my personal copy it will be so
RE: IizR14 - fuirippu - 03-12-2015
Hmmm... ZR... now I want one.
RE: IizR14 - greatgamer34 - 03-12-2015
It literally is address 000 and always outputs 0.
RE: IizR14 - Magic :^) - 03-12-2015
basically don't hook up a read to address 000
RE: IizR14 - Chibill - 03-12-2015
Don't hook anything to 000
RE: IizR14 - greatgamer34 - 03-12-2015
Don't have any physical memory at address 000 lol
RE: IizR14 - fuirippu - 03-12-2015
Now, I'm disappointed...
I like my programs to start at 0
I want a ZR and mem address 0 !!!
RE: IizR14 - Magic :^) - 03-12-2015
register address 0, not program address xD
so then if you did $000 + $000,
and saved to $001
the value in $001 would be 0
RE: IizR14 - LordDecapo - 03-12-2015
#derail
#ZRftw
RE: IizR14 - fuirippu - 03-13-2015
Sorry... ZR is my new thing.
(03-12-2015, 09:49 PM)The Magical Gentleman Wrote: register address 0, not program address xD
Good. If it's gonna be called a register, I don't want it using up PROM or nothing !!!
Unless... hmmm.... are you trying to memory-map me out of my rightful share of bytes?
RE: IizR14 - LordDecapo - 03-13-2015
#plznoderail
Any posts about that actually thread? LoloL
Gotta love OREs derail abilities
RE: IizR14 - Curiosity85 - 03-15-2015
What does the IS in IizR-IS stand for?
RE: IizR14 - Chibill - 03-15-2015
Instruction set
RE: IizR14 - LordDecapo - 03-16-2015
Yup lol
RE: IizR14 - LordDecapo - 03-31-2015
So guys, i finally am officially posting stats for IizR14. i have solidified most of these to be final. Only a couple things here and there are subject to change.
-6tick clock (goes to 8 during serial transmissions, since I use 1tick/bit serial)
-6 stage pipeline
-128bytes of RAM(runs via Bytes and 8byte Pages so it can be connected to external storage)
-16-32 byte L1 cache (depending on ticks required)
-32memory mapped locations
-software and hardware based interrupt and exception support
-7 serial hardware ports (16bit sub addressing supported) with 1 being keyboard, 2 being network and 3 being display, so 4 universal ports.. all with interrupt support.
-8bit data width
-256lines of PROM
-64byte Instruction Cache (for external Inst. memory)
-16bit external Instruction addressing support with full Call and Return support.
-19bit external Data storage support (16bit page addressing, each page has 3 bit sub address delt with after a page is in RAM)
-And some more stuff I probably forgot to put in
The IS so far is this:
![[Image: ASg6E0U.png]](http://i.imgur.com/ASg6E0U.png)
The IS has some stuff that needs addressing and is subject to change, but this is it so far.
As i am closer to completion then ever, i will be making paperwork for this CPU on how it functions, how the individual ops will flow through the pipeline, and how the kernel/PROM will arranged. As the PROM will be used for built in functions that u can call to from a program stored externally.
so ya
here it is, xD
RE: IizR14 - Chibill - 04-01-2015
COOL!!!!!!! your CPU might be used to make the first dual-core Computer in MC (where both cores are working on different stuff). AKA MCX!
RE: IizR14 - LordDecapo - 04-01-2015
lol, its possible, but it wont be made for that at the get go
i will have multiple connected via network, but the closest thing to it being dual core currently is that memory access is handled by a DMA like device, so i can have loads/stores to/from external hardware run solo of the CPU main core
that being said,, if i modified my Cache layout and a couple other things, then a dual core wouldnt be TOO hard, just be annoying
RE: IizR14 - Chibill - 04-04-2015
How would you change what page of ram your on.
RE: IizR14 - LordDecapo - 04-06-2015
(04-04-2015, 11:21 PM)Chibill Wrote: How would you change what page of ram your on.
Well my addressing will take care of that.
when you use an address to access RAM (16 pages of 8bytes,,, 128 bytes total).. It will depend on if you are using RAM to interact with the CPU or external storage. If you are using external storage interface (page based) the addressing will ignore the lower 3 bits of the 7, giving you the upper 4 bits to address the 16 pages. To which u address a page in external (external is addressed based on pages, so you never choose which byte,just the page the byte you want is in) Memory.
example:
Import 4-167 13 *3
will take Sector 4, page 167,168,169 (3 of them since it's *3). And put it in RAM pages 13, 14, 15.
I you are using RAM with the CPU then u only address the RAM by bytes.
some sections of the memory outside of that 128 are special cases, so they are a bit funky.