So I haven't done much here lately, but when I saw this I thought of redstone

[CreepyTacoMan]

So, there's this thing called mill architecture.

http://en.wikipedia.org/wiki/Mill_CPU_Architecture

Basically, the idea is that in the CPU, rather than storing data in registers in static locations wherever it fits, this stores it at the beginning, and then advances all the other data down 1 register. What this does is dramatically increase the write speed of cache while reducing complexity, while hopefully not lowering read speed.

Obviously there are challenges with this, such as having a way of tracking data, but if anything it would just be a neat project, regardless of performance.

What are your thoughts on this?

[greatgamer34]

Seems similar to a belt cpu.

IDK what a belt is, I have just overheard others talking about one.

[Chibill]

http://millcomputing.com/docs/

[Magazorb]

you should do your research on the mills CPU, it's no quicker in cache writing due to the belt register, it's quicker to write cache because it calls it before it requires it thus preloading it into cache, that was the biggest let down of x86 based architectures, Mill architecture has been known for a while now, and all the challenges you think it presents are taken care of by the compiler, it has a lot of downsides the mill architecture and on of them is that IRL with the stages given in the example it wouldn't go much above 1GHz if you was lucky.

there is no 1 basic idea with the mill architecture as it implements many new architectural changes compared to x86 based architectures, what you described is just a standard CPU with a belt register instead, which by it's self yields no performance gains and high chance of data corruption.

[Chibill]

But would it help in Minecraft for speed. Even if not IRL?

[Magazorb]

It would have some advantages and disadvantages, but for any well skilled redstoner i don't think it would make much of a difference, it would bealbe to be smaller as you can just use shift registers modified to have a read mech at least on devices that will only make one register write per clock.

also this could easily be made to give a quicker clockspeed on single staged PEs as there's no delay selecting which register to write to, but this can be overcome by a simple forwarding system anyhow.

The mill architecture has lots of advantages and is well worth looking up, it's very educational and gives you a good insight on the shortfalls of more conventional designs, definitely worth while learning about.

[LordDecapo]

GG, mill IS THE BELT architecture lol, like they came up with it and are the only company with it lol.
also, the 1ghz is only the 1st generation.. the amount of actual logic in the system is SUBSTANTIALLY less then any competitionso OOOexe/SS designs. So I forsee these speeds sky rocketing once they get the funds to get down to the print size that Intel or AMD has.
The only issue with belt is it requires a LOT MORE COMPLICATED compiler since it has to take care of ALL dependencies and other issues.

[Chibill]

But would this help redstone speed up? (Like say we built whole computers with terminals and everything.)

[Magazorb]

and of course it's compiler dependent much more so then other architectures which grants many unique issues.
tbh i doubt Mill or Mill based architectures will ever get much quicker, they patented all of it off and aren't going to develop any systems themselves, meaning if you want to use their stuff not only will you have to pay for licencing and royalties but you'll have to engineer the product your self with very limited support.

The Mill architecture has it's ups and down just research about it and from it what you can.
but it's pretty much a CPU that's specialized in running with high PE count with many vering branches.
Would probably make for a killer Gaming CPUs if it was programed for and less compiler dependant.

[Jallen]

But would this help redstone speed up? (Like say we built whole computers with terminals and everything.)

It generally won't help if we were to try and implement the system in minecraft. The main issue being the fact that we'd have to make a really complicated pre runtime compiler to actually use it with any usability. There is also the fact that most of the benefits are completely removed by the fact that we generally only use one FU in current CPU designs. If you added more adders/other units and implemented a system that uses VLIW type instructions then it might be helpful. This is because it's speed comes from its ability to handle 33(if I remember correctly) mixed MIPS instructions which is impossible with only a single ALU and no other FUs.