01-07-2015, 06:52 PM
(This post was last modified: 11-23-2015, 03:47 AM by Magic :^).
Edit Reason: updated everything a bit
)
./warp cca
video here: https://www.youtube.com/watch?v=FrWNrTTcdXg
NOTE: There have been massive improvements to the CCA design, so I may redo this OP at some point. So there will be some trimming done to this post, and I'll probably do a tutorial post on how to build one in a new thread.
First, I'd like to say that Yap7 also came up with the same type of carry logic independently of myself a few months later, before joining ORE. I figure he deserves just as much credit as I do for coming up with this style of addition.
- for future reference, my original design was created in September 2014
How it works:
The adder is comprised of 3 stages:
In stage 1, the adder performs XOR, AND, and NOR.
XOR is pretty straightforward. It's just the sum without the carry.
AND is the Generate signal G.
NOR is the Carry Cancel signal CC.
In stage 2, the G and CC signals are sent to two separate slab stacks. The G signal goes to a slab stack that connects to the base input of every comparator in the CCA carry tower. The CC signal goes to a slab stack that connects to the side input of every carry tower comparator.
When these signals hit the slab stacks, you need to provide full power (15 signal strength). The carry calculation works in ratios of signal strength so make sure that your input strengths are all the same! Also keep in mind that these slab stacks are supposed to 'bleed upwards' to the other comparators, that's the core of how this system works.
The two slab stacks are used by a comparator at each level to calculate whether there is a valid carry. The G signal is what is passed through the comparator, and the CC signal is what goes into the side for comparison. If the signal strength read from the CC stack is higher than the signal strength from G, the carry is 'cancelled'.
This works because a physically higher CC will always have a higher signal strength than a G signal from below.
The same goes for if G is stronger than CC, it can only mean that G happened at least 1 level higher than CC. This would force signal out of the comparator as the CC signal can't subtract it all. This comparator's output would signify that a carry happened, and needs to be XORed in stage 3.
In stage 3, the output of the comparators of stage 2 are fed into a final XOR with the first XOR result from stage 1. The output of this XOR is the final result.
In summary:
Stage 1: xor, and, nor. (2 ticks)
Stage 2: carry calculations. (1 tick)
Stage 3: final xor. (2 ticks) (This can be 1 tick with a special type of XOR I designed)
Now here's the example adder:
First, here's a top-down view of the adder. The blue part is stage 1, the white is stage 2, and the yellow is stage 3. Green is the signal source for AND/Generate, and red is the signal source for NOR/Carry-Cancel.
![[Image: 9wHWSTZ.png]](http://i.imgur.com/9wHWSTZ.png)
In stage 1 to create the AND, I NOR the 1 tick XOR and NOR using the existing circuitry. I then add 1 tick to the NOR and XOR to sync with the AND. (that makes 2 ticks in total.)
The nor is on the far right.
![[Image: z6ACLsM.png]](http://i.imgur.com/z6ACLsM.png)
Here's a close-up of the comparator that does the carry calculations. Note the difference in signal strength here where G>CC. That's allowing the carry to go through as G happened above CC.
![[Image: eiMRkw5.png]](http://i.imgur.com/eiMRkw5.png)
(For later comment context, this post was originally on what this adder design should be called)
video here: https://www.youtube.com/watch?v=FrWNrTTcdXg
NOTE: There have been massive improvements to the CCA design, so I may redo this OP at some point. So there will be some trimming done to this post, and I'll probably do a tutorial post on how to build one in a new thread.
First, I'd like to say that Yap7 also came up with the same type of carry logic independently of myself a few months later, before joining ORE. I figure he deserves just as much credit as I do for coming up with this style of addition.
- for future reference, my original design was created in September 2014
How it works:
The adder is comprised of 3 stages:
In stage 1, the adder performs XOR, AND, and NOR.
XOR is pretty straightforward. It's just the sum without the carry.
AND is the Generate signal G.
NOR is the Carry Cancel signal CC.
In stage 2, the G and CC signals are sent to two separate slab stacks. The G signal goes to a slab stack that connects to the base input of every comparator in the CCA carry tower. The CC signal goes to a slab stack that connects to the side input of every carry tower comparator.
When these signals hit the slab stacks, you need to provide full power (15 signal strength). The carry calculation works in ratios of signal strength so make sure that your input strengths are all the same! Also keep in mind that these slab stacks are supposed to 'bleed upwards' to the other comparators, that's the core of how this system works.
The two slab stacks are used by a comparator at each level to calculate whether there is a valid carry. The G signal is what is passed through the comparator, and the CC signal is what goes into the side for comparison. If the signal strength read from the CC stack is higher than the signal strength from G, the carry is 'cancelled'.
This works because a physically higher CC will always have a higher signal strength than a G signal from below.
The same goes for if G is stronger than CC, it can only mean that G happened at least 1 level higher than CC. This would force signal out of the comparator as the CC signal can't subtract it all. This comparator's output would signify that a carry happened, and needs to be XORed in stage 3.
In stage 3, the output of the comparators of stage 2 are fed into a final XOR with the first XOR result from stage 1. The output of this XOR is the final result.
In summary:
Stage 1: xor, and, nor. (2 ticks)
Stage 2: carry calculations. (1 tick)
Stage 3: final xor. (2 ticks) (This can be 1 tick with a special type of XOR I designed)
Now here's the example adder:
First, here's a top-down view of the adder. The blue part is stage 1, the white is stage 2, and the yellow is stage 3. Green is the signal source for AND/Generate, and red is the signal source for NOR/Carry-Cancel.
In stage 1 to create the AND, I NOR the 1 tick XOR and NOR using the existing circuitry. I then add 1 tick to the NOR and XOR to sync with the AND. (that makes 2 ticks in total.)
The nor is on the far right.
Here's a close-up of the comparator that does the carry calculations. Note the difference in signal strength here where G>CC. That's allowing the carry to go through as G happened above CC.
(For later comment context, this post was originally on what this adder design should be called)
![[Image: 96432320150108090117.png]](http://img4.hostingpics.net/pics/96432320150108090117.png)
![[Image: 98977120150108090101.png]](http://img4.hostingpics.net/pics/98977120150108090101.png)
![[Image: zBG0Apc.png]](http://i.imgur.com/zBG0Apc.png)
![[Image: 2tlbewN.png]](http://i.imgur.com/2tlbewN.png)
![[Image: 3vTGE66.png]](http://i.imgur.com/3vTGE66.png)
![[Image: XmiGiA9.png]](http://i.imgur.com/XmiGiA9.png)
![[Image: dTxHiq0.png]](http://i.imgur.com/dTxHiq0.png)
![[Image: lMkEB0n.png]](http://i.imgur.com/lMkEB0n.png)
![[Image: YvjQsAD.png]](http://i.imgur.com/YvjQsAD.png)
![[Image: wwwg5IB.png]](http://i.imgur.com/wwwg5IB.png)
![[Image: wPExEny.png]](http://i.imgur.com/wPExEny.png)
![[Image: 11kzPyq.png]](http://i.imgur.com/11kzPyq.png)
![[Image: corpse.jpg]](http://img.photobucket.com/albums/v191/legofreak1988/avy-sig/corpse.jpg)
![[Image: US5487025-6.png]](https://patentimages.storage.googleapis.com/pages/US5487025-6.png)
![[Image: US06367059-20020402-D00005.png]](https://patentimages.storage.googleapis.com/US6367059B1/US06367059-20020402-D00005.png)
![[Image: Zo6kZFW.png]](http://i.imgur.com/Zo6kZFW.png)
