Such high-tech!
Non-volatile data storage based on detecting stackable vs non-stackable items in chest inventory. Fully working model.
Specs:
Capacity 27 bit.
Write single binary string, max 1b/0.4s.
Read full content, constant 1b/0.4s, optional pause.
Erase all and sort items, optional pause/stop.
I/O are modulations of signal strength and -length, more on that in the world download.
Multiple devices tileable sideways, effective 4 block width per device.
World download (transparent model with user guide signs included):
https://www.dropbox.com/s/lpueukqcywszed...2.zip?dl=0
Here shown to the right of experimental analog delay line RAM.
![[Image: rUbC2M2.png]](https://i.imgur.com/rUbC2M2.png)
Transparent model.
![[Image: 6dXT5YD.png]](https://i.imgur.com/6dXT5YD.png)
Operation instructions.
![[Image: Qk3c4I6.png]](https://i.imgur.com/Qk3c4I6.png)
Very tileable. Much parallell.
![[Image: HK88PlL.png]](https://i.imgur.com/HK88PlL.png)
EmpirerBAD©
Non-volatile data storage based on detecting stackable vs non-stackable items in chest inventory. Fully working model.
Specs:
Capacity 27 bit.
Write single binary string, max 1b/0.4s.
Read full content, constant 1b/0.4s, optional pause.
Erase all and sort items, optional pause/stop.
I/O are modulations of signal strength and -length, more on that in the world download.
Multiple devices tileable sideways, effective 4 block width per device.
World download (transparent model with user guide signs included):
https://www.dropbox.com/s/lpueukqcywszed...2.zip?dl=0
Here shown to the right of experimental analog delay line RAM.
![[Image: rUbC2M2.png]](https://i.imgur.com/rUbC2M2.png)
Transparent model.
![[Image: 6dXT5YD.png]](https://i.imgur.com/6dXT5YD.png)
Operation instructions.
![[Image: Qk3c4I6.png]](https://i.imgur.com/Qk3c4I6.png)
Very tileable. Much parallell.
![[Image: HK88PlL.png]](https://i.imgur.com/HK88PlL.png)
EmpirerBAD©