Instant Comperator Carry adder

[minestyler007]

I recently made a new kind of adder that I call Instant Comperator Carry (ICC). It uses a carryline which consists of many comperators whos outputs go into the side input of the next one. By powering all the back inputs they become not gates and every second comperator will be turned off. There is a bug which makes comperator calculate the side inputs instantly if the back input is 1 tick before the side input. Like that you can make a signal travel through all the not-gates within 1 tick. The downside is that you have to sync the inputs and activate it for example with a CPU clock.

For the adder I use XNOR and AND for the carry generation just like in ICA. And another XNOR for the output. 2 Comperators create 1 bit. The ANDs output goes to the comperator that is off by default and the XNOR goes into the comperator that is on by default. Carryin is true if the comperator, that is usually off, is on. 

advantage: pistonless
downside: needs synced inputs, is kinda big and  uses XNORs so I only got it to 6 ticks.

I see some more potential in it as you can use ICE logic and use NAND and NOR for the generate and propagate that would get it to 4 ticks. 

Another thing i see is that you could further exploit the bug to create a 1 tick adder by only using clocked comperator not-gates.

The problem is that I'm kind of new and dont have the knowledge to build this ( I tried it for quite some time). so i hope someone can help me and that i explained it ok. If you have questions - just ask.

UPDATE: I found a pretty cool thing which would allow this adder to be ANY bit size without adding extra delay. it works by only activating the back inputs if a signal has to be propagated through the output of and XOR. it is superhard to implement so I couldn't  make it. it also does not need synced inputs and does not need to be clocked. it is at min 5 ticks or maybe 4??? anyways i think it would rather work with 7 or 8 ticks but that would still be pretty good for something like 512 bits

[PNWMan]

*Is there a /warp to see it?
*How many bits can this make without adding delay in the carry line?

Sounds like a cool concept, I'd love to check it out and see if it can be smaller and faster so it can be a new option for adders.

[minestyler007]

I made a warp : /warp ICC

for now there were some really annoying things that just didnt work.
the adder is 4 bit but i think that it can be expanded to 8 bits by doing i more compact. this design could be 8 bits but I'm not sure. one problem was that, even though the signals of the 5th to 8th bit reached at the same time as the first to 4th bit, only the first 4 were without ripple. i think there are some things i have to test to make it it possible.

also my 6 bit one just wouldnt work for some reasons i dont understand as it was setup exactly like a slower one i built... 

It would be really great if we could maybe work on this together.

[minestyler007]

ok i just managed to build an 8 bit one

[Magic :^)]

this is a pretty cool thing you've come up with. The 1 tick precharge thing might not be too much of an issue once it's in a CPU because you could easily sync that with your clock, and synced inputs are the norm anyways. I might have a go at making an adder of this design soon, I'll post here if I come up with something good.

[LambdaPI]

Not practical in le pipelined CPUs as koyarno showed me. Still cool idea, kinda similar to my 3 tick bcs that used dat comparator glitch. I really am looking forward to seeing this, cause I can't for another 25 days.

[LambdaPI]

Mm. One problem I think I see tho. The comparators still have 1 tick each, you can't make them instant. It's just that the side inputs can change the output instantly if they are 1 tick later than the main input. So, you can't make a string of not gates calculating in 1 tick. I think... ?

[minestyler007]

well you can make a not-gate chain ... that works fine and was the first thing i was testing when going into building this adder. I found 2 more porblems: it can't be extended infinitly - i think -because it loses 1 signal strength every bit :/ that has to do with another bug these comparators have where you can't have the back inputs all the same strength. another thing i'm experiencing is that it sometimes just wouldn't work... not in single cases but in some designs. I tried to build another version of my first adder and it did not work. I'm pretty sure it is not timing as i counted the ticks and also tried every other timing... I don't really know why thats happening and how it could work. I definetly have to do more testing.

[LordDecapo]

That comparator bug won't work if your trying to make a fully sync system. When used in a carry it will make 1/16 situations of the adder be 1 additional tick.
This is the same reason why the "solid state 3tick CCA" is "3 1/16ticks"... or 3 15times, and 4ticks 1 time.

Love the adder idea, just wanted to let you know about the idiocy with that glitch

[LambdaPI]

If you want, you can check out this thread, where I used the side input comparator glitch. Maybe it'll give you some new ideas. Good luck

https://forum.openredstone.org/showthread.php?tid=9186

[minestyler007]

hmm i didnt experience that it would be one additional tick...
i still dont get CCA i think I'll have to learn it at some point.

anyways there are some new cool things i found out. you dont have to sync the inputs because the bug will also work if the inputs came before the back input as it has to calculate the first side input in 1 tick and then will give the output which will make the other comparators become their side inputs one tick later so it will still calculate everything without delay.

i also found out that you can expand it infinitly - as long as the back inputs are still synced. I'm not too sure about it as i tried it in my singleplayer world which is 1.8.
I don't have internet often so i can't test it on the server

[minestyler007]

So i finally managed to make a kind of good adder... it is 8 ticks and has a useless doubleinversion that i didn't get rid off because i was super annoyed by this shit because it took me about 15 tries to make it work but all  in all I'm quite happy with how it worked. the carry line never dies out but you have to power the back inputs of the comparator line all at once.

I also found a new way for the carry propagation. it would not need the back inputs to be powered by a cpu anymore nut still need synced inputs AND at least 1 tick of all zero between every calculation.

It works as follows: AND for generate and XOR for propagate. the xor will be connected to the back inputs of the carry - line comparators. so the comparators would only have there back inputs activated if they could propagate.

i found out that it works if it propagates but it ripples if it DOESN'T propagate. but i think you could get rid of this.

pictures: http://imgur.com/a/Q217O

also it can be 4 ticks if someone is able to make a 1 tick xor that you can stack 2 wide (actually it's 2 wide and diagonal but a kind of horizonatl diagonal...)

[GISED_Link]

seriously ? F3 F1 THEN F2 is really this hard to press ??????????

Anyway this thing is interesting

[minestyler007]

sorry realized that thats annyoing too but too late...

[minestyler007]

i built another adder which is 7 ticks and uses the new way for carrying

http://imgur.com/a/666Yg

some things i found:

• works best if the comparators face south (north is ok 2 but had this ripple thing for the very last comparator).
  

• the back inputs have to be powered with redstone dust that is full signal strength and that is powered by redstone torches
  

• if you power it in a different way you have to have every second comparator have less signal strength then the one before which leads to signal strength loss of 2 power per bit.
  

[Apocryphan]

uh, good luck solving the directional issue, i had started to map out the working directions of some 1 tick circuits, but there is more to consider than we realize, like chunk position, even when its fully within the chunk i've had 2 identical circuits behave differently. but this is still neat, it reminds me of a hybrid between analog and binary.

[Apocryphan]

here are some of my notes when i was attempting to decipher the directional issue. inputs with red wool do not work and ones with green do. these are all 1 tick pulsers if you ever need one, try these.






And here is something that may help when timing 2 signals to meet.

[josh03222]

acro stahp bumpin

[Chibill]

Josh at least unlike your bumps his are productive...

[josh03222]

Josh at least unlike your bumps his are productive...

thats because all of my bumps were in shenanigans (except for that ONE TIME where i didnt know bumping was a thing and i only had forums account for like a week or two