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+---- Thread: Instant Comperator Carry adder (/thread-10204.html)
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Instant Comperator Carry adder - minestyler007 - 07-02-2016
I recently made a new kind of adder that I call Instant Comperator Carry (ICC). It uses a carryline which consists of many comperators whos outputs go into the side input of the next one. By powering all the back inputs they become not gates and every second comperator will be turned off. There is a bug which makes comperator calculate the side inputs instantly if the back input is 1 tick before the side input. Like that you can make a signal travel through all the not-gates within 1 tick. The downside is that you have to sync the inputs and activate it for example with a CPU clock.
For the adder I use XNOR and AND for the carry generation just like in ICA. And another XNOR for the output. 2 Comperators create 1 bit. The ANDs output goes to the comperator that is off by default and the XNOR goes into the comperator that is on by default. Carryin is true if the comperator, that is usually off, is on.
advantage: pistonless
downside: needs synced inputs, is kinda big and uses XNORs so I only got it to 6 ticks.
I see some more potential in it as you can use ICE logic and use NAND and NOR for the generate and propagate that would get it to 4 ticks.
Another thing i see is that you could further exploit the bug to create a 1 tick adder by only using clocked comperator not-gates.
The problem is that I'm kind of new and dont have the knowledge to build this ( I tried it for quite some time). so i hope someone can help me and that i explained it ok. If you have questions - just ask.
UPDATE: I found a pretty cool thing which would allow this adder to be ANY bit size without adding extra delay. it works by only activating the back inputs if a signal has to be propagated through the output of and XOR. it is superhard to implement so I couldn't make it. it also does not need synced inputs and does not need to be clocked. it is at min 5 ticks or maybe 4??? anyways i think it would rather work with 7 or 8 ticks but that would still be pretty good for something like 512 bits
RE: Instant Comperator Carry adder - PNWMan - 07-02-2016
*Is there a /warp to see it?
*How many bits can this make without adding delay in the carry line?
Sounds like a cool concept, I'd love to check it out and see if it can be smaller and faster so it can be a new option for adders.
RE: Instant Comperator Carry adder - minestyler007 - 07-03-2016
I made a warp : /warp ICC
for now there were some really annoying things that just didnt work.
the adder is 4 bit but i think that it can be expanded to 8 bits by doing i more compact. this design could be 8 bits but I'm not sure. one problem was that, even though the signals of the 5th to 8th bit reached at the same time as the first to 4th bit, only the first 4 were without ripple. i think there are some things i have to test to make it it possible.
also my 6 bit one just wouldnt work for some reasons i dont understand as it was setup exactly like a slower one i built...
It would be really great if we could maybe work on this together.
RE: Instant Comperator Carry adder - minestyler007 - 07-03-2016
ok i just managed to build an 8 bit one
RE: Instant Comperator Carry adder - Magic :^) - 07-05-2016
this is a pretty cool thing you've come up with. The 1 tick precharge thing might not be too much of an issue once it's in a CPU because you could easily sync that with your clock, and synced inputs are the norm anyways. I might have a go at making an adder of this design soon, I'll post here if I come up with something good.
RE: Instant Comperator Carry adder - LambdaPI - 07-05-2016
Not practical in le pipelined CPUs as koyarno showed me. Still cool idea, kinda similar to my 3 tick bcs that used dat comparator glitch. I really am looking forward to seeing this, cause I can't for another 25 days.
RE: Instant Comperator Carry adder - LambdaPI - 07-05-2016
Mm. One problem I think I see tho. The comparators still have 1 tick each, you can't make them instant. It's just that the side inputs can change the output instantly if they are 1 tick later than the main input. So, you can't make a string of not gates calculating in 1 tick. I think... ?
RE: Instant Comperator Carry adder - minestyler007 - 07-06-2016
well you can make a not-gate chain ... that works fine and was the first thing i was testing when going into building this adder. I found 2 more porblems: it can't be extended infinitly - i think -because it loses 1 signal strength every bit :/ that has to do with another bug these comparators have where you can't have the back inputs all the same strength. another thing i'm experiencing is that it sometimes just wouldn't work... not in single cases but in some designs. I tried to build another version of my first adder and it did not work. I'm pretty sure it is not timing as i counted the ticks and also tried every other timing... I don't really know why thats happening and how it could work. I definetly have to do more testing.
RE: Instant Comperator Carry adder - LordDecapo - 07-06-2016
That comparator bug won't work if your trying to make a fully sync system. When used in a carry it will make 1/16 situations of the adder be 1 additional tick.
This is the same reason why the "solid state 3tick CCA" is "3 1/16ticks"... or 3 15times, and 4ticks 1 time.
Love the adder idea, just wanted to let you know about the idiocy with that glitch
RE: Instant Comperator Carry adder - LambdaPI - 07-07-2016
If you want, you can check out this thread, where I used the side input comparator glitch. Maybe it'll give you some new ideas. Good luck
https://forum.openredstone.org/showthread.php?tid=9186