03-19-2015, 12:54 AM
you should do your research on the mills CPU, it's no quicker in cache writing due to the belt register, it's quicker to write cache because it calls it before it requires it thus preloading it into cache, that was the biggest let down of x86 based architectures, Mill architecture has been known for a while now, and all the challenges you think it presents are taken care of by the compiler, it has a lot of downsides the mill architecture and on of them is that IRL with the stages given in the example it wouldn't go much above 1GHz if you was lucky.
there is no 1 basic idea with the mill architecture as it implements many new architectural changes compared to x86 based architectures, what you described is just a standard CPU with a belt register instead, which by it's self yields no performance gains and high chance of data corruption.
there is no 1 basic idea with the mill architecture as it implements many new architectural changes compared to x86 based architectures, what you described is just a standard CPU with a belt register instead, which by it's self yields no performance gains and high chance of data corruption.