I am TSO

[LordDecapo]

NOTE: I am not calling you an idiot, and I am not telling you your design wont work, I am telling you from experience that your plans so far sound like it wil lbe a very slow computer, and unless you do pipelining then you are looking at a clock no faster then 40 or so ticks whilst current Redstone CPU's avg in the 20's.
And My own CPU being an 8tick clock, 8 staged pipelined, 16/32/48bit CISC IS, with full serial interface, Hardware stacks, and 105 total different arrangements of branch type/destination.
I started with the same enthusiastic intentions as you, and it will work for your better, but u will need to do some homework first and listen to others in this community for advice on what to do to make it faster.
Read my responses below with that in mind and at the end of this post I will attach a .rar file with a bunch of PDFs and PPTs I have on my laptop, if you would like more I can get them for you, as well as I know of a meriade of college lectures on Comp Sci. topics that can help you emensly,
Also I will include a Logisim version of my CPU so you know im not blowing smoke up your ass.
Feel free to ask me any questions.
and i hope you continue ur GO-GETTER attitude, i would love to have someone else to talk about advanced control units with on the server xD

First off, I'm well aware what an instruction set is, I'm just bad with acronyms. I have never referred to an instruction set as an, "IS," so when you said that, I thought there was an IS component unique to redstone computers or a component I gave a different name to.

IS is something that you will find that almost all college or more advanced places will refer to an Instruction Set, after doing a bit more research you will see IS a lot.
Another one that may help is Inst. which is just short for Instruction.

I have 44 operations I need this thing to perform, which is probably a lot more than any other minecraft computer, so I'll just call it CSIC. The actual opcodes aren't going to be created until after the computer is built, so that I can reverse engineer the whole system and have the codes mirror the processes that occur in the system, thus reducing the number of decoders.(I already know one typically does this the other way, buy my mind just doesn't quite work like that.) All I know is the first two bits of the opcodes, which will tell the CPU where to ship the information.

44 is ALOT, unless you have a HUGE IS that is just all your control lines bussed to one Program Memory bank, I highly recommend either finidng someones IS you like a lot on the server and then make yours based on there layout (only at first, you can change it 100%, but it will give you a great place to start) or you can throw together a quick one to make sure you have some of your CPU's functions predetermined,, it sucks adding a bunch of features to a CPU and realizing you only needed like 1/3 of them to actually do what all your IS needs.
An IS also helps define a lot of basic asspects of your CPU, making it almost a road map for how to build it with out ever touching hardware.

Memory space greater than 16 bits can easily be addresses using 16 bits and the secret sauce. Pointers are possible to write, but aren't needed, and not all the memory is registers or cache. There is an hierarchy that allows for addressing more than the bit space available to the word size. Although, I don't have a solution for fast registers yet...

how are you going to use more then 16bit addressing on a 16bit system? And be aware, you can make a CPU with as much memory as you want, but are you ever going to make a porgram that ACTUALLY uses it? Or could you program a tad bit better and have the program use your memory more wisely.

instant wire will fix bussing delays.
The Von Newman architecture is why it needs so much memory, and more secret sauce makes sure the computer has the program data as it's needed.

NO! instant wire bussing is a VERY VERY bad idea, I have seen many ppl (about half of which were long time MC CPU veterans) try and use it as one of those “cure all” solutions to bussing,, the timing will be hell, and you will end up wanting to pul ur hair out.
Also I personly dont ever use pistons.. in any CPU... ever... I hate them and there half tick nonsense and BUD glitches.. a Pistonless CPU (also called SS (Solid State) is much more predictible,
But if you like pistons and you want to use them, have at it just saying I personally dont like them at all.

The ALU uses some basic calculus

“basic” is a very HARD word here...
Cause calculus isnt something that is normally done at a MC CPU level, due to the massive amount of ticks it will add to your CPU, and if ur only using a basic ALU to do these,, there will be a lot of time that it will be clogged preforming the “basic” task of your calculus.

The entire system could use two's compliment floating point encoding for large integers, or it will use standard binary if told to.

2's comp is mainly for negitive, and floating point is decimal points (better known as Radix bits in binary) and you will need a good barrel shifter to be able to do FP well, I have a good design im working on if you want to use it.

And most importantly: more than one computer can use the memory without any issues. This is where the secret sauce really gets lathered on there.

2 CPUs with one memory is a bad idea,, only do it if you have a system to manage memory that is independent from the CPU's themselves, otherwise you will have addressing confilicts and data hazards, as well as architectural hazards (more then 1 data packet wanting to go down same bus line at same time, and other stuff)

I'm willing to bet a few of you already figured out what the secret sauce is made of, and the only reason it is even there is so that the computer can be programmed in a language other than machine code (like c or maybe just assembly), but I discovered that this single piece would allow for all of these other magical properties to suddenly be available because it would make the CPU itself run much faster because it only really has to do one thing now: move memory between registers or cache. This is a five(ish) tick process.

They may have but I have not figured this one out, but please tell me xD im curious.. and the way to make a CPU be able to be programmed in a higher lang, is by making a compiler and to have a GOOD IS that is small, yet feature rich, so you can easily port the coding in and out of the CPU's machine code.

I do suppose pipelining would be an option, but it would be more applicable toward the ALU than anything else. And this is just the first iteration anyway.

just saying the ALU is like the ONLY place you do not pipeline like ever, I mean you can yes, but due to speed limitations in MC, it doesnt give you any speed advantage, and to pipeline an ALU, you have to have a good hazard detection system and possibly OOOExe,, considering the delay of an OOOexe system,,, unless you make a milestone discovery it wont be beneficial to your clock speed/throughput.

@LD, the only thing there I've never heard of is OOOexe.

well dont worry, that is annoying as hell, I believe im the only one on the server that has made something using OOOexe, (the OOOexe stuff is in the Logisim CPU file I have linked in the bottom, however it isnt being used in the CPU at all, and it has some bugs that need to be fixed at some point if I ever decide to actually use it,,, but a Belt Architecture is better for consistency and such so I will be going that route)

Most of the instruction set actually just passes through the CPU, being routed to it's destination without any decoding at all.

well yes, all inst. Go though the CPU, xD that is what they are instructing and no.. u have to decode your Op's unless you want something so big that the straight control line programming will end up adding more delay then a simple decoder would have, and be about 5x the space

Upon consideration, I could venture to say that if you stood back far enough from it and squinted real hard, you would see something that sort of looked like a pipelined CPU.

doesnt work like that, either you are pipelined or your not,
the best way I would suggest you to get into pipelining is to do a 2 maybe 3 stage at first, and if you would like to do that, I can let you know the best way to go about that.

Also, just in case you still don't know the chunk loading thing I mentioned, I was talking about the spawn chunks. (Also, I had to look up what a command block was because I have never heard of them.)

this could work,, but a CPU is RARELY that big that it even comes close to going outside a render distance, and nothing outside the render distance (besides spawn chucks) even register when redstone is activated,, well they do SOMETIMES,, but its buggy enough that you can not use the system for a CPU as it wil corrupt data


Links as I promised:
Losgisim version of CPU
https://www.dropbox.com/s/df3e2wi82kftgt...4.rar?dl=0
This will have the CPU itself, the Instruction set and the 16/32/48bit framework exampled at the bottom of the IS, it also has the Logisim Program itself so u dont need anything else, and it has programs you can upload into the PROM in the CPU circuit, it is a work in progress and I am making a Belt version of the same IS shortly, after I finish porting that current version to MC (dropping data width from 16 to 8bit)
ask one of us if you are unsure how to use logisim

PDF and PPT resources
https://www.dropbox.com/s/j8ocf6aezj9uiu...s.rar?dl=0
these are not in any particular order and the naming system in them is dumb as hell (just left there names as they downloaded as) some are super advanced, some are mild, and some are simpler.. ull just have to go through them, let me know if you want stuff on a specific topic, and I can get you some great stuff on it.

As I said, im here to help, not to discourage

LAST NOTE: Bussing bro BUSSING,,, one of the most important things to keep In mind is “how do I minimize bussing time”. When making a CPU, you can have the fastest parts, but if your data loop has like 8 ticks of bussing delay,,, those are all wasted ticks,, that could either be eliminated, or that could be put to better use, like doing proccessing. So learn how to stack ur parts close as u can.