My asynchronous pipelined CPU, aka AsPipe

[Magic :^)]

I only have the data loop made, so alu ops, regs, and stack.
no ram, no branching, no prom

[TSO]

Yeah, like memory is the part that takes forever. You'll be done with that crap in like two hours. I time lined my computer at six months to a year.

[Magic :^)]

Yeah, I still have to finalise the protocols I'm going to use for my memory system. I'm thinking of dealing with hazards on a per-peripheral basis. So if a request is sent to a peripheral, it has its own hazard checking logic and will hold back the result until it is safe to do so. I figure it will be easier than having one BIG hazard detection unit. It also makes addressing via pointers easier, as the system I'm imagining only cares about physical addresses.

*shrug*

I may change that plan. It'll work itself out once I start building stuff.

[LordDecapo]

Anyways, I'm using microcode to translate 4-bit alu opcodes to the 5-bit codes it can interpret (I use the msb in my IS to indicate an alu op while in the main pipeline, so essentially 4-bit alu opcodes), so I can always replace one op with another with the slap of a torch

Hey I do that I love my 4bit Op and 1 bit OpMode :>


Also magical, Dylan Freemanz, and I looked at ur progress so far,, and we circle jerked on how much we liked it keep up the good work! Can't wait to see this done!

[Magic :^)]

I am grinning like an idiot

Oh yea, and the instructions are now being converted to 11 bit opcodes for the alu, it includes mode toggling and timing bits. The conversion still takes the same amount of time though (3 tick sync). I factor the decode/encode delay in to the timing section though, so the overall speed should still be pretty good.

IS update:

Code:

[{ifT}{3-bit flag adr}] [{jmp adr}] 01001xxx aaaaaaaa
[{ifF}{3-bit flag adr}] [{jmp adr}] 01000xxx aaaaaaaa
[{jump}] [{jump address}]           01010--- aaaaaaaa
[{call}] [{function address}]       01011--- aaaaaaaa
[{prog}{prog number}]               00010xxx
[{return}]                          00011---
[{halt}]                            00000---

[{read}{periph adr}] [{adr}]        01100xxx aaaaaaaa
[{ptrR}{ptr address}]               00111xxx

[{regread}{reg address}]            10000xxx
[{const}] [{imm}]                   01111--- aaaaaaaa
[{pop}]                             10010111
[{add}{to reg address}]             10100xxx
[{a-b}{to reg address}]             10101xxx
[{b-a}{to reg address}]             10110xxx
[{SHR}{to reg address}]             10111xxx
[{xor}{to reg address}]             11000xxx
[{xnor}{to reg address}]            11001xxx
[{or}{to reg address}]              11010xxx
[{nor}{to reg address}]             11011xxx
[{and}{to reg address}]             11100xxx
[{nand}{to reg address}]            11101xxx
[{!a}{to reg address}]              11110xxx
[{a}{to reg adr}]                   11111xxx

[{ptrE}{ptr address}]               10011xxx
[{ptrW}{ptr address}]               00100xxx
[{write}{periph adr}] [{adr}]       01101xxx aaaaaaaa

ALU microcode:

12 bit opcode: [if mode][3-bit control code][!a][!b][3-bit alu opcode][3-bit reg address]

the control codes with 0 as the msb are timing codes.
the other control codes are specific to the ops involved.

a/!a:       0 001 x0 001 aaa
nor/and:    0 001 xx 010 aaa
or/nand:    0 001 xx 011 aaa
xor/xnor:   0 010 x0 100 aaa
add/sub:    0 011 xx 101 aaa
SHR:        0 010 00 110 aaa

regread:    0 100 00 000 aaa
pop:        0 101 00 000 111
const:      0 110 00 000 ---
ptrE:       0 111 00 001 aaa

IFT/IFF:    1 000 00 000 aaa

[Magic :^)]

I uploaded screens to imgur. I am tired. Here:
http://imgur.com/a/PsWOb

[greatgamer34]

why no OCD pack?

[Magic :^)]

I'm getting on to that Don't you worry

[greatgamer34]

im working on a better resource pack based off of OCD, so it will be posted soon!

[Magic :^)]

Heyo, I got distracted on friday and wrote a compiler for my (not yet complete) processor. There are still a few bugs (like needing a \n at the end of the file, and only outputting to the console) but it is now compiling everything properly. I will post it once I give it some polish

for now, here's the fibonacci sequence in assembly to show the capabilities of the compiler:
(I know having an if statement in fibonacci is stupid, but it's there for illustrative purposes XP)

Code:

# Fibonacci sequence in assembly code.

###############
#    MACROS   #
###############

# Use the ! symbol to name a constant.

!overflow = $111 # labeling the address for the overflow flag bit
                 # for if statements.

# The $ symbol marks a 3-bit argument.

!x = $\1 # register one being named as x
!y = $\2 # register two being named as y

# Using a backslash will tell the compiler
# to convert a number to binary. It will know
# how many bits to convert to, and will tell
# you at compile time if the number is above
# the bit limit.

###############
#   ASSEMBLY  #
###############

# The @ symbol marks an 8-bit immediate.

con @\0 # load constant 0 to reg a
con @\1 # load constant 1 to reg b

# The ? marker refers to its assigned constant.

add ?x  # reg x = a + b
regR ?x # a = reg x
add ?y  # reg y = a + b

# The > marker is an address pointer. It assigns
# the address of the following instruction to the
# constant name next to it. The constant can be
# referenced by any instruction that takes an
# 8-bit immediate. It is most useful for branching
# statements, obviously.

>loopStart

regR ?x # a = reg x
regR ?y # b = reg y
add ?x  # reg x = a + b
ifT ?overflow @00000000 # restarts program if overflow detected.
regR ?y # a = reg y
regR ?x # b = reg x
add ?y  # reg y = a + b

ifT ?overflow @00000000 # restarts program if overflow detected.
jump ?loopStart         # otherwise loop. Essentially an if/else statement.

Oh if you're interested in how I made the compiler, it's written in Python, and reads the source file one character at a time in two passes: once to log the macro/meta stuff, and then again for a proper compile and error checking.