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+---- Thread: My asynchronous pipelined CPU, aka AsPipe (/thread-4837.html)
My asynchronous pipelined CPU, aka AsPipe - Magic :^) - 10-07-2014
Hello, MG here. I'm working on what functions to include in the ALU stage right now. I want to reduce the number of ops, but honestly I'm not sure what to get rid of. e.g. the nimplies ops.
BTW the following is a rough draft. In no way is this the finished list XP
Code:
Key: [word], {opcodes/arguments}, (generated words)
[{if}{3-bit flag address}] [{jump address}]
[{jump}] [{jump address}]
[{call}] [{function address}]
[{prog}] [{program address}]
[{return}]
[{halt}]
[{read}{3-bit peripheral addr}] [{8-bit address}]
[{ptr}{3-bit ptr address}]
[{register}{reg address}]
[{const}] [{8-bit immediate}]
[{pop}]
[{add}{to reg address}]
[{a-b}{to reg address}]
[{b-a}{to reg address}]
[{xor}{to reg address}]
[{xnor}{to reg address}]
[{or}{to reg address}]
[{nor}{to reg address}]
[{and}{to reg address}]
[{nand}{to reg address}]
[{a nimplies b}{to reg address}]
[{b nimplies a}{to reg address}]
[{!a}{to reg address}]
[{SHR}{to reg address}]
[{ptrW}{ptr address}]
[{write}{address}]
------------------------------------------------
general pipeline:
1. Branch processing block:
[{if}{3-bit flag address}] [{jump address}]
[{jump}] [{jump address}]
[{call}] [{function address}]
[{return}]
[{halt}]
2. Read processing block:
[{read}{3-bit peripheral address}] [{8-bit address}]
[{ptr}{3-bit ptr address}]
3. ALU processing block:
Loading to ALU:
[{register}{reg address}]
[{const}] [{8-bit immediate}]
({const}) ({8-bit immediate}) // converted from [{read}{}] instruction
[{pop}]
ALU ops:
[{add}{to reg address}]
[{a-b}{to reg address}]
[{b-a}{to reg address}]
[{xor}{to reg address}]
[{xnor}{to reg address}]
[{or}{to reg address}]
[{nor}{to reg address}]
[{and}{to reg address}]
[{nand}{to reg address}]
[{a nimplies b}{to reg address}]
[{b nimplies a}{to reg address}]
[{!a}{to reg address}]
[{SHR}{to reg address}]
Misc:
({if}{3-bit flag address})
Write ops:
Push to write block:
[{ptrW}{ptr address}] (a reg as physical address) (b reg as peripheral address)
if a & b registers loaded, and no other ops have been executed:
Push to write block:
[{write}{peripheral address}] (a reg as value) (b reg as address)
else:
[{write}{to reg address}]
4. Write processing block:
({write}{peripheral address}) (value) (address)
({ptrW}{ptr address}) (physical address) (peripheral address)RE: My asynchornous pipelined CPU, aka ASSPIPE - greatgamer34 - 10-07-2014
pick one subtraction op perferably a-b, get rid of the implies and get rid of the invert !a op.
if you want to invert a number going through the cpu, perform xnor on it, it will just invert it.
other than that it looks good!
RE: My asynchornous pipelined CPU, aka ASSPIPE - jxu - 10-07-2014
Asynchronous? But why??
RE: My asynchornous pipelined CPU, aka ASSPIPE - Magic :^) - 10-07-2014
(10-07-2014, 08:47 PM)͝ ͟ ͜ Wrote: Asynchronous? But why??
for the lolz ;P
Also, I like the challenge. Even if it ends up being ridiculously slow (hopefully not), I'll have learned something from it.
RE: My asynchornous pipelined CPU, aka ASSPIPE - TSO - 10-07-2014
Theoretically (again, one of my thought expiriments), one should be able to make a pipelined CPU where each clock cycle is actually triggered by the incoming program data, meaning it can run as fast as the data comes in. Thus, a clock is not needed, and it is therefore asynchronous.
Honestly, this sounds easier to build.
RE: My asynchornous pipelined CPU, aka ASSPIPE - Magic :^) - 10-08-2014
(10-07-2014, 11:10 PM)TSO Wrote: Theoretically (again, one of my thought expiriments), one should be able to make a pipelined CPU where each clock cycle is actually triggered by the incoming program data, meaning it can run as fast as the data comes in. Thus, a clock is not needed, and it is therefore asynchronous.
Honestly, this sounds easier to build.
That's exactly how I'm implementing it! Program data moves through the stages until the correct one is reached, and when the instruction resolves, the data is deleted and allows more instructions to fill the space left behind. In practice, that's a handshake protocol that requests and passes data along the pipeline as needed.
RE: My asynchornous pipelined CPU, aka ASSPIPE - TSO - 10-08-2014
Hmm... Sounds still a bit complicated. If data just kinda falls through the system, the data can force the system to process it at the exact rate it comes in. No saving is necessary if the instruction moves down the line with its data. All you need to do is use an edge detector and some delay equal to the delay of the operation being performed so that the detector just forwards the information to the next step once it has been calculated. When the instruction is completed, output data goes to memory, and instruction data just gets forwarded to nothing.
RE: My asynchornous pipelined CPU, aka ASSPIPE - Magic :^) - 10-08-2014
Here, I'll give you some of the relevant stuff I've looked up that will give you an idea of how the system will work:
I'm using a buffered asynchronous pipeline: http://en.wikipedia.org/wiki/Pipeline_(computing)#Implementations
A document that discusses the handshake protocols (Mine are MC optimized, not exactly the same):
http://www.cs.columbia.edu/~nowick/nowick-singh-ieee-dt-11-published.pdf
Here's another wikipiedia heading specifically on Asynchronous CPUs:
http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU
My processor will be along the lines of what is described there.
By the way, these were looked up post-inception of this idea, I basically learned the terminology from there more than anything else, and helped me make some small improvements to my original designs.
EDIT: Yeah, I used to use terms like 'self-governing queue' and other random terms. No-one understood me DX
RE: My asynchronous pipelined CPU, aka As-Pipe - Magic :^) - 10-09-2014
I updated the IS a bit:
Code:
Key: [8-bit word], {op field}
[{ifT}{3-bit flag adr}] [{jmp adr}] 01001xxx aaaaaaaa
[{ifF}{3-bit flag adr}] [{jmp adr}] 01000xxx aaaaaaaa
[{jump}] [{jump address}] 00001--- aaaaaaaa
[{call}] [{function address}] 00010--- aaaaaaaa
[{prog}] [{program address}] 00011--- aaaaaaaa
[{return}] 00100---
[{halt}] 00000---
[{read}{periph adr}] [{adr}] 00110xxx aaaaaaaa
[{ptrR}{ptr address}] 00111xxx
[{regread}{reg address}] 10000xxx
[{const}] [{imm}] 10001--- aaaaaaaa
[{pop}] 10010---
[{add}{to reg address}] 10100xxx
[{a-b}{to reg address}] 10101xxx
[{b-a}{to reg address}] 10110xxx
[{xor}{to reg address}] 10111xxx
[{xnor}{to reg address}] 11000xxx
[{or}{to reg address}] 11001xxx
[{nor}{to reg address}] 11010xxx
[{and}{to reg address}] 11011xxx
[{nand}{to reg address}] 11100xxx
[{!a}{to reg address}] 11101xxx
[{SHR}{to reg address}] 11110xxx
[{regwrite}{to reg adr}] 11111xxx
[{ptrE}{ptr address}] 10011xxx
[{ptrW}{ptr address}] 01100xxx
[{write}{periph adr}] [{adr}] 01101xxx aaaaaaaaRE: My asynchronous pipelined CPU, aka As-Pipe - greatgamer34 - 10-09-2014
Why have b-a along with !a as OPs?