Mini - Actual first CPU :P

[tokumei]

Related Links
Instruction Set

Type /warp DJ-Mini in chat to see the completed build!

This is a smaller project to help me ease back into CPU design, since the other one is very overwhelming. I'll be calling this project Mini, because it's a less-complicated 4-bit CPU based on my DJIS-8 instruction set. It will not have a data interface like the other one; instead it will have ROM for program memory.

Screenshots: Official Album

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Timeline

6/29/14 - Start date
7/01/14 - ALU completed
7/02/14 - Registers completed
7/03/14 - Program logic completed
7/04/14 - Synchronization completed
7/04/14 - Completion date

[tokumei]

Yesterday I finished the ALU. It is based on BlockandCube's 4-bit PLA adder, and has a throughput of 12 ticks (with 3 ticks of busing, so technically 9). The next component I need to tackle is the registers. I will probably use Nickster258's dual-read registers for the build, if I can't come up with a good design.

[tokumei]

As of today, the registers are now in place. I used a 4x2x17 dual-read design by Nickster258, with a 2-tick read and a 4-tick write speed. Up next: the program decoder! This is bound to be fun, since I reuse bits a lot.

Also, 1 small note: I made a warp that will bring you to the CPU - /warp DJ-Mini - if you are interested in looking at the design. Note of caution: I do not color-code anything.

[tokumei]

Another progress update: I have completed the program memory and logic systems. This completes the functional parts of the CPU; however it leaves the final and hardest step (in my opinion): synchronization. This may take another day or two to complete, but happily I'm at the point where I can take screenshots

[Chibill]

You work faster then me.

[Tjakka5]

We want pictures/demonstrations!

[tokumei]

Screenshots have been uploaded here: http://imgur.com/a/VENbM

[greatgamer34]

I feel as though for Solid State things, CLE is the way to go because recently Newo had a breakthrough in Dual read repeater lock registers, which are super fast and super small. And they OFC fit best with CLE.

Congrats on your build though! keep us updated!

[tokumei]

Okay, as of now the CPU is clocked and ready to go... except for one small problem: Because of the delay between the program decoder and the brancher, conditional branching is quite unstable and takes up 2 lines/branch to be stable. It can probably be fixed with a change in the clock speed, or some kind of speed optimization. I will mark this as a complete project, but beware of that timing glitch.

[greatgamer34]

make it a 2 stage clock. Simple when you get a branch instruction, the clock will take 2 cycles to complete it. You can use a simple PC, that once it reaches 2, it the updates the master PC.
So all instructions take one cycle, so in the first PC once it hits 1, then it updates the master PC,
Then you have your branch instruction, which takes 2 clock cycles. so the first PC will have to hit 2, before it updates the master PC.

[Ntwede]

make it a 2 stage clock. Simple when you get a branch instruction, the clock will take 2 cycles to complete it. You can use a simple PC, that once it reaches 2, it the updates the master PC.
So all instructions take one cycle, so in the first PC once it hits 1, then it updates the master PC,
Then you have your branch instruction, which takes 2 clock cycles. so the first PC will have to hit 2, before it updates the master PC.

Exactly what gg said. In fact, the pc only has to be 1 bit. That's how my CPU worked.

[greatgamer34]

exactly sir ntwede!