05-12-2018, 12:14 AM
(This post was last modified: 05-12-2018, 12:29 AM by PaukkuPalikka.
Edit Reason: test
)
hi
so i mad this dual core pipe line'd 4 tick latch clock with intelgated cpu and gpu with xy decoder. control unit and 1 bit rom., uses an ica data loop alu
which is connected to the second core and gpu
picture's:
a quick over view with fea't.uring my fan's:
\warp nocpu
first core with ica carry adder and data loop
secon'd core and part of gpu with big resolution display
high tech gpu with fast
almost forgo't to say that swift helped my with this project a bit with the RCA and others were very supportive too thanks
gpu pipe data line with loop buffer latch register
con trol unit,, and clock with 1 bit ROM for bIG user programs!
All attackments are embedded above
can be moved to shenanigans sometime
so i mad this dual core pipe line'd 4 tick latch clock with intelgated cpu and gpu with xy decoder. control unit and 1 bit rom., uses an ica data loop alu
which is connected to the second core and gpu
picture's:
a quick over view with fea't.uring my fan's:
\warp nocpu
first core with ica carry adder and data loop
secon'd core and part of gpu with big resolution display
high tech gpu with fast
almost forgo't to say that swift helped my with this project a bit with the RCA and others were very supportive too thanks
gpu pipe data line with loop buffer latch register
con trol unit,, and clock with 1 bit ROM for bIG user programs!
All attackments are embedded above
can be moved to shenanigans sometime