7 ticks 8 bit CPU

[Bejro]

I have just finished my CPU. It got some fancy features, for example you can create up to 4 registers in RAM. However, it works wierd, It got 10 registers (A,C and r1-r8) and if you are making some ALU operation it takes A and currently active r-sth register and saves the result in C. It can relocate pretty much of registers data but you can't move A anywhere (You can sum it with 0 to save it to C) and you can't move r-sth to C. It can also generate some random noumber (4 bit or 8 bit). I can write about some more features if you'd like to.  http://imgur.com/a/xB5ir

[LambdaPI]

looks hot.

Can it branch?

And them pistons. I hate on pistons.

[LambdaPI]

Jk i don't hate on pistons, I just don't use them.

[Bejro]

So what can I use instead of pistons?

[CrazyGuy108]

Eww, instalogic!
*throws up*
jk
Looks really compact. Any details on instruction set/architecture?

[LambdaPI]

creycrey ur da one who used to use instalogic

[CrazyGuy108]

creycrey ur da one who used to use instalogic

jk

[Bejro]

It's 100% my architecture. The main thing is switch that make the CPU compute something or pass all the data through to the other units like GPU. It got 34 functions. Like jump/jump if, save data from RAM/register/user to some register, basic logic functions, 3 main flags (<>=), and also sending register data out of the CPU. It could have 6 logic gates but it uses only 3, that's because of gate negator which is not connected (I don't really think i will use XNOR or NAND). That's all, I think.

[CrazyGuy108]

It's 100% my architecture. The main thing is switch that make the CPU compute something or pass all the data through to the other units like GPU. It got 34 functions. Like jump/jump if, save data from RAM/register/user to some register, basic logic functions, 3 main flags (<>=), and also sending register data out of the CPU. It could have 6 logic gates but it uses only 3, that's because of gate negator which is not connected (I don't really think i will use XNOR or NAND). That's all, I think.

Cool. Is there like a google doc or something that u can put the ISA on? Doing something like that (or just making an ISA board on your plot) is usually a good practice for documenting your build.

[Bejro]

I have something ISA-like in my notebook, That helps me write programs. If you wnat to I can make some digital version too. Anyway, I've just finished! http://imgur.com/a/qN1UL

[LordDecapo]

Can u set a warp to this? I'd love to see it
Is it pipelined,,, how have I not talked to u before? Lol

[Bejro]

I'm playing single player so it'd be hard to set a warp xd. I can't really say if it's pipelined, maybe kind of but not really.

[Matthew]

lol sounds pretty cooleo

[Bejro]

I have looked into this project again and now I fully understand the issue of this CPU and pipelining. It is not pipelined, yet it is. I don't know everything about how CPUs works thus I made it work my own way. In classic pipelining every step (decoding coputting and so on) takes full clock cycle, however, not in my processor. In my creature during 8 ticks instruction is being decoded computed and the result is saved in proper register. So that, I could say that it is 2 tick not pipelined processor or 4 times pipelined 8 tick processor. I don't really know, nevertheless, This CPU can't embrace multiple operations at the same time (except some exceptions like jump if operations or accesing to RAM treating it like cache).

[Koyarno]

It is fine as long as anything your cpu does not do anything "undefined"; like that you know if you did a conditional branch, how many instructions after it get executed regardless of you taking the branch or not.

Did you make anything in the meantime or thought about some concepts you learned?

[Bejro]

I feel like I'm done with minecraft computers like for now. So that, I didn't make anything lately :c. The cause of it would be that current versions of minecraft simplify redstone in order to avoid lags and my CPU can't work anymore (can only if I play old versions).

[Koyarno]

yes, i strayed away from pistons primarily because of blockdrops that happened in the earlier days. But even though they do not happen now? anymore they are still affected by both changes in redstone mechanics & block mechanics. I do not use anything that is proven unreliable. I've got a 6 tick solid state cpu but it was a pain to build.

[Bejro]

Sorry for not respondig your question about branaching. If you want to take conditonal branch you have to previously make some comparioson which result (boolean) is being saved to "branching 1 bit register". Then, you ask CPU to do condiotional branch and after that you insert new address. If conditon is True CPU swiches address instantly (during same cycle) or if not address is loaded from RAM but none of the CPU parts is awaiting for data so that it changes nothing. Currently I have made new CPU, intended to be just working on my computer. It is somehow simpler somehow more ergonomic. one cycle takes 1 second but in order to avoid bugs duration is incresed to 1.8 second. It is working and I have finnished (and tested) Fibonacci sequence generator, that includes branching and takes only 10 Bytes.

[LordDecapo]

nice nice, where is this build?
You may be interested to see how i do my stalling and branch logic in my current HRM CPU build.

[MumboJumbo]

Anyone have a good Alu I can take inspirating on? I have designed adders and ram..... but can't get it to wire up good, I know, this is a noob thing to ask but I need it

[LambdaPI]

Anyone have a good Alu I can take inspirating on? I have designed adders and ram..... but can't get it to wire up good, I know, this is a noob thing to ask but I need it

Fyi it would be nice to create another thread instead of posting in a basically unrelated one.

[Bejro]

nice nice, where is this build?
You may be interested to see how i do my stalling and branch logic in my current HRM CPU build.

I'm building anything very rarely and I'm using, as I said before, old minecraft version with world edit. However I could make and share some file with my world.