07-16-2020, 12:19 AM
elastic synchronous architecture is when a synchronous system is designed using some qualities of asynchronous circuits to allow it to be more flexible when it comes to data latencies and allows the clock period to be faster than the slowest circuit.
What I’m suggesting Is a CPU architecture where various systems, such as the ALU, have a clocked delay line set up using a shift register, with its delay(in clock cycles) being equal to that circuit’s slowest possible performance, with the output only being retrieved once a completion signal makes it to the other end of the delay line. This could allow a CPU to run faster since it’s clock speed is no longer constrained to that of the slowest possible data path.
I’m just throwing this out their in case anyone wants to use the idea
What I’m suggesting Is a CPU architecture where various systems, such as the ALU, have a clocked delay line set up using a shift register, with its delay(in clock cycles) being equal to that circuit’s slowest possible performance, with the output only being retrieved once a completion signal makes it to the other end of the delay line. This could allow a CPU to run faster since it’s clock speed is no longer constrained to that of the slowest possible data path.
I’m just throwing this out their in case anyone wants to use the idea
