07-22-2017, 08:56 PM
Well, I could not finish, IRL stuff got in the way :/
Here is some explanation anyway of ALURAM™
The idea behind my contraption was to use the Negation occuring at read from memory to perform logical functions, if I read from two cells at the same time, I have NAND, which, combined with a Shifter is all that is needed to perform any logical function. So my ALU pretty much is just a Shifter (perhaps the only one that actually has a shifter (?)), the rest being implicit.
There would be 1 Byte of RAM dedicated to PC purposes, I decided on a simple Shift one, that way, since next line can be loaded from memory, branching is achieved. There would have been 8 adressable ROM lines, however, there would be multiple instructions on each line, delayed, at the end of each adressable line, implicit excecution of next line (from dedicated PC Byte), which allows function-like callability. 7 Bytes of RAM total, 8th activates Shifter, since there are only 8 Bytes, there is no need for a memory controller, and since there are 8 adressable lines of ROM, no need for "ROM controller", and since instructions share adress space with memory (and only 8 adressable adresses), no need for decoding instructions either.
In the end it turned out to be pretty huge, my only hope would have been if RAM and ROM did not count towards size, but I think my realistic goal was to get it working.
Thank you PaukkuPalikka and Jonay for providing me a way to participate when I had no access to neither the school server nor the build server by accepting me to the school server in no time
Here is some explanation anyway of ALURAM™
The idea behind my contraption was to use the Negation occuring at read from memory to perform logical functions, if I read from two cells at the same time, I have NAND, which, combined with a Shifter is all that is needed to perform any logical function. So my ALU pretty much is just a Shifter (perhaps the only one that actually has a shifter (?)), the rest being implicit.
There would be 1 Byte of RAM dedicated to PC purposes, I decided on a simple Shift one, that way, since next line can be loaded from memory, branching is achieved. There would have been 8 adressable ROM lines, however, there would be multiple instructions on each line, delayed, at the end of each adressable line, implicit excecution of next line (from dedicated PC Byte), which allows function-like callability. 7 Bytes of RAM total, 8th activates Shifter, since there are only 8 Bytes, there is no need for a memory controller, and since there are 8 adressable lines of ROM, no need for "ROM controller", and since instructions share adress space with memory (and only 8 adressable adresses), no need for decoding instructions either.
In the end it turned out to be pretty huge, my only hope would have been if RAM and ROM did not count towards size, but I think my realistic goal was to get it working.
Thank you PaukkuPalikka and Jonay for providing me a way to participate when I had no access to neither the school server nor the build server by accepting me to the school server in no time