03-20-2016, 04:42 AM
So true. I see student after student building the same thing: RCA ALU. Many normally fail their first or second trial because they don't understand certain concepts, such as the use of FC and 2's complement.
Raising the standard to a lookahead adder like CLE/CCA/CSA would only add another layer of memorization. The properly taught people pass, sure, but the majority of them only know the design and a handful of concepts that apply to it. The next thing I see from them is usually a mass of wires called a control-line CPU (Even I was a victim of this routine when I passed my trial), even on their student plots before a trial, or annoyingly asking around for help on building an actual CPU.
Making the minimum a dataloop, instead of a more advanced adder, would better prepare students for the more intensive projects of Build. All you need to add is an instruction set, pROM, control unit, and PC (All of which should be simple enough if you already know how to build a decent data loop) and you have a decent CPU. The disadvantage is a longer trial period, which, with a small amount of staff actually willing to trial and with the recent flood of visitors/students, will not be favorable.
I kind of have a mixed position on this. Though it would be preferable to have a more advanced ALU as the minimum, there's no 100% stopping this kind of issue.
Raising the standard to a lookahead adder like CLE/CCA/CSA would only add another layer of memorization. The properly taught people pass, sure, but the majority of them only know the design and a handful of concepts that apply to it. The next thing I see from them is usually a mass of wires called a control-line CPU (Even I was a victim of this routine when I passed my trial), even on their student plots before a trial, or annoyingly asking around for help on building an actual CPU.
Making the minimum a dataloop, instead of a more advanced adder, would better prepare students for the more intensive projects of Build. All you need to add is an instruction set, pROM, control unit, and PC (All of which should be simple enough if you already know how to build a decent data loop) and you have a decent CPU. The disadvantage is a longer trial period, which, with a small amount of staff actually willing to trial and with the recent flood of visitors/students, will not be favorable.
I kind of have a mixed position on this. Though it would be preferable to have a more advanced ALU as the minimum, there's no 100% stopping this kind of issue.