10-07-2014, 04:36 AM
Examination indicates an eight bit Von Newman machine stacked on itself three times and given the same clock.
Information moves counterclockwise through this system, starting from memory on the left.
There are three layers of 64 bytes of memory (thus 192), each layer corresponds to one of the three ALU units. At any read, one of the eight values in one of the eight chunks is selected. All three memory layers are read to the ALU at the same time. Either the bottom line contains program memory that can be altered, making this a full Von Newman machine, or there is program memory under the main memory. Of note: memory is stored in inverted form.
It appears that once the three data lines arrive, MSB on left, the corresponding data stream to ALU level forms the first operand, I can't tell where the second comes from, but the ALU itself can either bit mask them, bitwise OR, or add the two streams, carrying right to left, then upward. It is an RCA ALU. Data leaves the ALU and goes back to main memory, which is all clocked together.
If there is a memory level interchange between the three, it is on the output of the main memory, but I don't think there is.
I think the ALU is still incomplete, seeing as how the second operand isn't present.
Information moves counterclockwise through this system, starting from memory on the left.
There are three layers of 64 bytes of memory (thus 192), each layer corresponds to one of the three ALU units. At any read, one of the eight values in one of the eight chunks is selected. All three memory layers are read to the ALU at the same time. Either the bottom line contains program memory that can be altered, making this a full Von Newman machine, or there is program memory under the main memory. Of note: memory is stored in inverted form.
It appears that once the three data lines arrive, MSB on left, the corresponding data stream to ALU level forms the first operand, I can't tell where the second comes from, but the ALU itself can either bit mask them, bitwise OR, or add the two streams, carrying right to left, then upward. It is an RCA ALU. Data leaves the ALU and goes back to main memory, which is all clocked together.
If there is a memory level interchange between the three, it is on the output of the main memory, but I don't think there is.
I think the ALU is still incomplete, seeing as how the second operand isn't present.