12-17-2015, 02:52 AM
Saw a design of something like this on someone's plot. Sorry, but I can't remember the name
. I took it into my plot and me and Burgled compacted it quite a bit. The result was a 1224 block (17*8*9) 4-bit decoder. Here are some screenshots.
http://imgur.com/a/Apyga
Should be important to note that the dual-edge monostables weren't included in the block count, as "that can be done in cpu control logic".
![Sad Sad](https://forum.openredstone.org/images/smilies/sad.png)
http://imgur.com/a/Apyga
Should be important to note that the dual-edge monostables weren't included in the block count, as "that can be done in cpu control logic".