CMOSprinkle's Super Compact Redstone Computer!

[CMOSprinkles]

Hello everyone! I'm really hoping that people are more interested in this here then at the other forums. I'm building a redstone computer! What will this computer do? Whatever you can program it to do! That's right, a programmable redstone computer that you can write your own programs for. The PC uses a vertical shift register I designed that can easily perform conditional and unconditional branches when you want with a minor modification. I won't release the computer itself until I have written the first program for it to properly display it's functionality. Once the first program is finished (I'm thinking about working on a 'Cherry Drop' game or Pong) and the computer is available, I'll give you a list of the OPcodes used as instruction lines for the Programs and you can even write your own programs! The computer runs at a speed of approximately 0.67 hertz, or 40 instructions per minute, or 12 tick clock cycles. The components that I have built so far are the CPU, the program memory, and the PC. The Program Counter is actually going through some final design stages that I have to prepare a program for, so rather than writing a basic program in the meantime, I'll just wait until the first game for the computer is written and test it with that. My main concern at the moment is the GPU, which I will most likely be building myself, as I have not seen any designs yet that I like. So, the GPU could take some time, but you can expect the full release of the computer and the first game to be programmed within a month, so look forward to it! CMOSprinkle's Super Compact Interactive Vanilla Redstone Computer, COMING SOON!

[newomaster]

Ooh sounds like it's going to be awesome Ive actually never seen anyone run software pong. I'm excited to see if you pull it off.

[CMOSprinkles]

Alright, progress has been slow because my laptop is a piece of junk. I'm still working with the GPU, and the algorithms for the Pong game are really complex, so it will take some time to implement. I'll try to keep you guys updated, still hoping for the initial release in one month!

[CMOSprinkles]

Just a little update, the screen for the computer is finished! However, it isn't exactly a GPU, as it can't draw or save complex images. The only way that I can imagine implementing a GPU to draw entire images would be to write to the screen one line of pixels at a time, which would be horrendously slow at this computer's clock speed. Perhaps someday I will design a computer fast enough to update entire images on screen for sprite based games, but for now nobody wants to wait 10 seconds to see their character move. So this screen will only be able to run extremely simple games that only utilize one row of pixels at a time. However, I am also building in a 'controller input' to the screen that will utilize a shift register to display the player's "character" in the game as well as an AND gate hit detection circuit that will affect the branching conditions in the program to allow the player to interact with the game. The first game I will be working on will be 'Cherry Drop', where the goal is to catch the falling 'cherry'. If you catch it, the program will loop and drop another one; if you don't catch it, the program will end. Extremely simple stuff here, but it takes a lot of complex circuitry. But don't worry, I'll eventually work my way up to more complex games and programs!

[CMOSprinkles]

Just a small update here; No one saw the PC I was working on, and let's just say that's a good thing. I misunderstood the concept in a way that lead me to design a very inconvenient branching system, so I am likely going to end up using someone else's design for the PC as well, unless I can design a smaller binary counter.

P.S. Don't tell anyone, but after this super compact computer is finished, I'm going to design... *dun dun dun* *pause for suspense*... The 1 Hertz Computer!! It's basically going to be a modified version of this that is a bit larger, but will run on 8 tic clock cycles, so it will be capable of doing not only more than this, but much faster! Spoilers ;D

[CMOSprinkles]

Hello again, just wanted to say that with the one month deadline looming, it doesn't look like this computer is going to be finished in time. However, I have completely dedicated myself to building it to run on 10 tick or less cycles, or 1 Hertz. It's going to utilize a 3-4 tick instant carry adder that I am designing right now, I'll put the adder up on my plot when it is finished for anyone that is interested!

[Chibill]

I may be itersated in la adder. For what I am working on next.

[CMOSprinkles]

Well apparently someone beat me to it about a year ago. I just recently found a download for a 3 tick insta-carry adder created by some user called 'Whiteley'. I took a look at it and it blew me out of the water, it has some pretty advanced piston logic. I noticed there might be a BUD affecting the pistons at the very bottom, since this was made about a year ago, but I didn't do extensive testing and it could probably be fixed pretty easy if it was even causing an issue. Here's a link to the MCEdit schematic I found, couldn't find anything else; http://www.mediafire.com/?cswsgq57s7e13v0

[EDevil]

Thats a very interesting design! However, its kinda big. Especially compared to this design, from Matt Youtube!, which is basically the same, but way smaller. And if you're really looking for speed, and your inputs are in sync, i have a 2-tick adder for you, but its bigger than the design mentioned above. Ow, and btw, i really like is how you keep this topic up to date! Good work!

[CMOSprinkles]

Yeah, I did notice that Whiteley's adder is pretty huge, 15 blocks tall is a bit ridiculous. I don't think a 2 tick instant-carry adder is possible because it would have to generate the carry in 1 tick, but if it is possible I would love to see your design! I'm actually continuing work on mine, I think it's finished. It uses a 2 tick half adder I designed myself that supports instant-carry and a 1 tick XOR designed by Properinglish19, I'll try to put it up on my plot later today. It's only 7 blocks tall, but it's about 26 blocks long, so it's still pretty big. However, generating any 8 bit result in 3 ticks is pretty damn impressive.

[CMOSprinkles]

Ok, I finished the final design and the entire 3 tick adder is 22Lx2Wx8H, obviously not very compact. However, it is much more compact than Whiteley's 20Lx2Wx17H 3 tick adder! I'll add a download link here soon, provided that my computer doesn't overheat. I know that it will overheat if I try to build the adder on my plot, so maybe I'll try that later tonight when my computer has had time to cool down.

[CMOSprinkles]

Bad news, Minecraftforum user Jxu had apparently already come up with the 2 tick half adder I designed quite a while ago. His half adder generates the carry in 3 ticks, but it's practically the same design as mine and can be made to generate the carry in 2 ticks by using my method. He also managed to compact it to 4 long, so the Adder he designed is only 12 blocks long. Even though I modified it, I'm giving credit for the design entirely to him since he most likely already knew how to modify the carry and chose not to for size. So I apologize for the plagiarism and I will remove the adder from my plot when I get home tonight. This brings my plot back to being entirely empty, apart from my unidirectional vertical shift register which is not very impressive, so that's a bummer. Work is continuing on the computer though, I'm going to use Jxu's Adder along with Minecraftforum user Aelond's 3 tick Universal Logic Gate to make the ALU. That's the next big update, and it's coming soon, so keep checking for new updates on the computer!

[Billman555555]

Hey CMO, Nice Designs, Specially the Adder.
After I Have Finished SAC Can U Possibly Help Me On SAC 2, Its Going To Be Faster, Meaner and Cooler *Literally*(Lots Of Ice). Anywho Can You Help Me Make SAC 2 Possibly 0.75 Hz, Maybe 0.8. If Not Don't Hesitate To Tell Me.(Also Thanks For The Help On The SAC Fourm ).
Thanks, Billman555555

[VirtualPineapple]

You say its going to be programmable, what type of architecture are you going for to modify programs 'interactively' (Von Neumann or Modified Harvard)?. Also what is your desired memory capacity overall on the computer (Registers, RAM, external storage)?

[CMOSprinkles]

I'm using the typical Von Neumann architecture for this at the moment. I suppose that could change if I run into issues with the bottleneck, though I think that 10 ticks should be a reasonable goal even for a Von Neumann computer. As for the interactive element, I'm still working on how to support that. It will have something to do with the GPU's hit detection and it may involve a flag register. As for the memory; the CPU will have 4 General Registers as well as an 8 byte stack. The main memory will be expandable, instant wiring will make expansion simple, and I will look into memory mapped I/O as soon as I get the chance. The Program Memory will also be expandable in the same way. How many bytes of each I put in will depend on what I need for my programs, but I will probably start with something like 64 bytes of each. I will be using the swapping technique to save space in the main memory. These are just some of my goals with this computer, but it is still a long way from being finished. I'm still debating using a RISC instruction set, I don't like the way that some functions have to be executed by using multiple instructions. Thanks for the questions, feel free to keep them coming!

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Hey Bill, your post must have sneaked in there, I didn't see it before. I would be happy to help with SAC or SAC 2! I may not have any solid designs for hardware components yet, but I am always willing to help with designing the architecture. If speed is your goal, I can tell you how fast each component needs to be, and I'm sure I can assist if you need help making any of the components function more quickly.

[CMOSprinkles]

Hey, just in case anyone is still watching this thread, just want to let you know that the reason production has stopped temporarily is because I am having major overheating issues with my laptop. I hope that soon I will be able I resume work again, my CPU v3 is going to be the next release (whenever that is) and it is going to be completely RISC compatible, much faster and more powerful than versions 1 and 2.

[Xeomorpher]

._. Hope you fix it!

[Billman555555]

I'm using the typical Von Neumann architecture for this at the moment. I suppose that could change if I run into issues with the bottleneck, though I think that 10 ticks should be a reasonable goal even for a Von Neumann computer. As for the interactive element, I'm still working on how to support that. It will have something to do with the GPU's hit detection and it may involve a flag register. As for the memory; the CPU will have 4 General Registers as well as an 8 byte stack. The main memory will be expandable, instant wiring will make expansion simple, and I will look into memory mapped I/O as soon as I get the chance. The Program Memory will also be expandable in the same way. How many bytes of each I put in will depend on what I need for my programs, but I will probably start with something like 64 bytes of each. I will be using the swapping technique to save space in the main memory. These are just some of my goals with this computer, but it is still a long way from being finished. I'm still debating using a RISC instruction set.

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Hey Bill, your post must have sneaked in there, I didn't see it before. I would be happy to help with SAC or SAC 2! I may not have any solid designs for hardware components yet, but I am always willing to help with designing the architecture. If speed is your goal, I can tell you how fast each component needs to be, and I'm sure I can assist if you need help making any of the components function more quickly.

Thanks good luck with 1 hertz,
Also I have slowed production on SAC and SAC videos due to
Stufz but I can help on this if you need anything done.
Also I recommend asking Craftriot about OISC, he is developing
It to help MC computers to advanced to the next speed.

[CMOSprinkles]

I'm assuming that stands for 'Optimal Instruction Set Computing', which is a very bold claim to make. Although, I also assume that it would be identical to MISC, 'Minimal Instruction Set Computing', which is a concept that has been done. Anyway, send me a link to his thread about it and I will look into it. If he does not have a thread for it, ask him to make one. Thanks Bill!

[Billman555555]

I'm assuming that stands for 'Optimal Instruction Set Computing', which is a very bold claim to make. Although, I also assume that it would be identical to MISC, 'Minimal Instruction Set Computing', which is a concept that has been done. Anyway, send me a link to his thread about it and I will look into it. If he does not have a thread for it, ask him to make one. Thanks Bill!

Close it stands for Optimised instruction set computing,
Utilising IS that are less than 48 bits in length but behave
Like RISC instructions, A+B for example in CISC might take
2 or 3 instructions but in RISC or OISC it takes 1 instruction.
SAC utilising OISC has 40 or so bits of IS per line.

[CMOSprinkles]

You have that backwards; a CISC would take less instructions to operate and it would be capable of doing 2 or 3 operations in a single instruction at the cost of severely reduced speed. Looking at the thread about 'OISC', it more closely resembles CISC than RISC.

[Billman555555]

* Billman555555 facepalm

[CMOSprinkles]

Out of curiosity, anyone know if a 1 tick write RAM module is possible?

[Billman555555]

Out of curiosity, anyone know if a 1 tick write RAM module is possible?

Yea if using a piston BUD or basil flop it's 1.5 ticks and a peater lock
Is 1-2 ticks.

[CMOSprinkles]

Repeater locks are 3 ticks, 1 for the locking repeater to change state, another for the locked repeater to change state, then a third for the locking repeater to save that state. At least that is what I believe should be the case, I wouldn't mind seeing some screenshots that prove otherwise. Anyways, I know that 1.5 ticks is possible (Bazil Flops write in 1.5 ticks), I was just curious if there is a true 1 tick write RAM out there.

[Billman555555]

Repeater locks are 3 ticks, 1 for the locking repeater to change state, another for the locked repeater to change state, then a third for the locking repeater to save that state. At least that is what I believe should be the case, I wouldn't mind seeing some screenshots that prove otherwise. Anyways, I know that 1.5 ticks is possible (Bazil Flops write in 1.5 ticks), I was just curious if there is a true 1 tick write RAM out there.

A locked repeater will need 1 tick to invert, 1 Tick to lock, the data
Is 1 tick but is counted separate because it changes as the input changes
I will get on ingame and take A photo later.

Btw: impossible to be 1 tick write.

[CMOSprinkles]

Actually, I have an idea. Use the retracting state of a piston (which is instant) to allow a wire input to a Bazil Flop. Then you only have to count 1 tick for the torch inverting the piston, 1 tick write. In theory, haha, but it should work.

[Billman555555]

I was going to try that but I realised it wouldn't work as the flop
Would change to 0 when the piston extends. 1.5. Ticks is about the
Smallest you can go.

[CMOSprinkles]

Hm, maybe if when the input is high and the clock goes high, the piston will stay retracted and only be allowed to extend when the input is low and the clock goes high. That would also keep the output from pulsing, so I will work on that idea.

[CMOSprinkles]

I believe I've done it; I used a NOR latch even faster than the one the Bazil Flop uses, so by using the instant state of a piston moving a block and a 1 tick repeater delay, it actually achieves a 1 tick write. Check it out in the Completed Projects subfolder.

[Billman555555]

Nice work CMO, I might use the RAM but I think I'll stick to
Nicksters peater lock system and the read I put on it.

[CMOSprinkles]

Production is postponed indefinitely, I'm not sure that I will be able to continue working on this at all. It was fun the few times that I could hop onto the server, so thank you everyone. Feel free to delete my plot, it's unlikely that I will be able to return to the server anytime in the next year or so. Thank you for your help and support with this project, I look forward to seeing the 1Hz computer done by someone else, I've heard that there is at least one other in the works!

[Guy1234567890]

D: whai you leave?

[CMOSprinkles]

I'll still lurk the forums as I always have, but in truth I was only able to get on the server maybe three times including my trial. My computer just can't handle the processing. So really, nothing is changing, haha.

[Guy1234567890]

Ah right. Well, hopefully you get the hardware so you can come on some time!

[Billman555555]

CMO look in the off topic discussion.

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For the lazy:
http://openredstone.org/forums/showthread.php?tid=674