5 tick 16 bit solid state adder

[Cutlassw30]

For a while I have been needing a 16 bit adder for a von neumann CPU I will be making. One issue, I hate pistons. So I needed some type of solid state 16 bit adder. Ripple carry was out of the question (even at 1 tick per bit). Block ripple carry look ahead and Carry block look ahead are good ideas but are also a tad too slow for my tastes (around 8-10 ticks). So CLE right? well turns out 16 bit CLE is not fun at all and also CLE is a completely difference form factor than im used to working in. So I said ok I will make CLA, LFA to be exact. Well that too was too slow as LFA has 2 tick BK cells (2 ticks is as fast as you can get a pure BK cell). So I started looking at PLA (Proper Lookahead Adder, named by properenglish as he published it first on youtube). Now I knew it was 4 ticks for 8 bits but I got worried about about 16 bits. So I researched it a bit (started messing around on my plot) And I figured it would only be 1 more tick for 16 bits. That's 5 ticks in total so I started out on a adder adventure. And this is the result.

Size:
per bit size: 2 wide per bit.
L*W*H: 32*36*13

Specs:
Type: Parallel prefix binary addition module.
Speed: 1/2 second (5 ticks).
Throughput: 3 hz (3 ticks).
Word size: 16 bits
Cin and cout?: Yes
Clock type: Asynchronous
Output noise: Mid zero
Sync execution: Yes


One thing to note this adder has a noisy output, that means that will give 4 output states. zero, High, low, mid zero.
Mid zero just means that the output signal is slightly on, this is no issue as its only 3 blocks. These blocks are taken into account in the Length
measurement.
But anyways who am I stalling? pictures!








-Cutters

[newomaster]

Ooh fancy What exactly is the difference between a "Proper look ahead adder" and an LFA. Does it take advantage of some CLE logic to reach later bits while still using mostly BK cells? (This is how I've heard it)

[Cutlassw30]

Ooh fancy What exactly is the difference between a "Proper look ahead adder" and an LFA. Does it take advantage of some CLE logic to reach later bits while still using mostly BK cells? (This is how I've heard it)

PLA logic uses a lot of things. For one it uses 1 tick BK cells in alternating inverted inputs and inverted outputs. Then it combines the first and second stages into 1 stage. And it dose use CLE carry lines for the propagate calculations.

[properinglish]

I was just looking through the forums and saw this - just wanted to say it made me smile. Nice work cut!

ps. I made a more compact 1 tick XOR a few months back - I will build it on the server for anyone who's interested.

Edit: And newo, to add to what Cut said - it uses NOR to control carry propagation so that the first half adder is effectively one tick. It also takes advantage of a trick that Darkroom came up with that allows NAND to be used so that the third layer is 1 tick. The result in an 8 bit PLA is 1 tick for the half adder, 1 tick for the first two layers of lookahead, 1 tick for the third layer of lookahead, and 1 tick for the XOR on the end.

[Chibill]

Hay proper! :-)

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Also his hard would it be to make this into a ALU.

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Also his hard would it be to make this into a ALU.

[CMOSprinkles]

Wow, I didn't know you were a member here Proper. I just wanted to say that, in general, I really like your creations, you've made some excellent innovations in the Redstone industry. Also, if you have pics of that more compact 1 tick XOR, I'd love to see it. My issue with the comparator XOR is that it requires a certain signal strength to go in, too weak and it won't output. In most cases, this leads to a repeater of some kind being necessary. Anyways, excellent work with the adder Cutlass, good use of Proper's XOR there.

[properinglish]

Haha yeah, I just signed up yesterday to say hi and tell cut that I was happy to see him playing around with PLA. And thanks!!! I can't really add pics right now (on vacation and about to head to the beach! ), but yesterday I built a 4 bit version on the POL near the other XORs. It's 2 wide/bit (with overlapping bits - technically a 3 wide unit), 7 long, 6 tall, and has an output signal strength of 11 - so not too shabby!

Chi - like most CLA variations it should be just as easy as making any other ALU, although I never bothered to turn a PLA into one because most of what I built didn't require an ALU.

[CMOSprinkles]

The output signal strength is nice, but my concern is the input signal strength. If you could put the signal in at ~strength 7 and still get at least a signal strength 1 output, that would be pretty impressive!

[CMOSprinkles]

Hey Proper, I came up with a new XOR design. I don't know if you are even still monitoring the forums here, but if you are interested, here's some specs:

Dimensions: 7 long * 2 wide * 6 tall; each bit is technically 3 wide, but can be staggered 2 wide
Speed: 1.5 Ticks
Signal Strength: Accepts minimum 5 signal strength in and outputs at 12

I also made a 1.5 tick XNOR that is 1 tick on the rising edge and quite compact at 5*2*6. I don't have access to a computer, so I'll try to upload some nice hand drawn schematics tomorrow for some friendly ORE member to possibly throw together and take a picture.