08-17-2014, 09:18 AM
(This post was last modified: 08-17-2014, 09:19 AM by LordDecapo.)
Yo, so the same project i have been working on for ever on the server, then went on and off a private server with; has gone into LogiSim and MC now.
So;
I will have an 8bit Data "3T" (Thrown Together Tester) one in MC, to test out the IS decoder and such and programs on ORE with out major lag. This version will have a 2 stage pipeline; as to avoid dependencies and to make building it much quicker.
I will have the same version in Logisim but 16bit Data, for Same testing purposes.
After that testing i will be making a higher stage count and faster clock version in MC, after i see how lag effects the test build.
Around the same time as that version i will be making a Quad core version that uses an additional command which makes the IS VLIW (Very Long Instruction Word) friendly. This command will be NoOp'd out in both of the MC versions, as MC is to bugging for that much shit. lol
The IS they Use will be;
for MC and will be CISC
For LogiSim and will be a VLIW/CISC hybrid.
Ill be posting all related stuff here for the builds so check back
So;
I will have an 8bit Data "3T" (Thrown Together Tester) one in MC, to test out the IS decoder and such and programs on ORE with out major lag. This version will have a 2 stage pipeline; as to avoid dependencies and to make building it much quicker.
I will have the same version in Logisim but 16bit Data, for Same testing purposes.
After that testing i will be making a higher stage count and faster clock version in MC, after i see how lag effects the test build.
Around the same time as that version i will be making a Quad core version that uses an additional command which makes the IS VLIW (Very Long Instruction Word) friendly. This command will be NoOp'd out in both of the MC versions, as MC is to bugging for that much shit. lol
The IS they Use will be;
for MC and will be CISC
For LogiSim and will be a VLIW/CISC hybrid.
Ill be posting all related stuff here for the builds so check back