IizR-ISx16 ISA "family" - Printable Version +- Forums - Open Redstone Engineers (https://forum.openredstone.org) +-- Forum: ORE General (https://forum.openredstone.org/forum-39.html) +--- Forum: Projects & Inventions (https://forum.openredstone.org/forum-19.html) +---- Forum: In Progress (https://forum.openredstone.org/forum-20.html) +---- Thread: IizR-ISx16 ISA "family" (/thread-4423.html) |
IizR-ISx16 ISA "family" - LordDecapo - 08-17-2014 Yo, so the same project i have been working on for ever on the server, then went on and off a private server with; has gone into LogiSim and MC now. So; I will have an 8bit Data "3T" (Thrown Together Tester) one in MC, to test out the IS decoder and such and programs on ORE with out major lag. This version will have a 2 stage pipeline; as to avoid dependencies and to make building it much quicker. I will have the same version in Logisim but 16bit Data, for Same testing purposes. After that testing i will be making a higher stage count and faster clock version in MC, after i see how lag effects the test build. Around the same time as that version i will be making a Quad core version that uses an additional command which makes the IS VLIW (Very Long Instruction Word) friendly. This command will be NoOp'd out in both of the MC versions, as MC is to bugging for that much shit. lol The IS they Use will be; for MC and will be CISC For LogiSim and will be a VLIW/CISC hybrid. Ill be posting all related stuff here for the builds so check back RE: IizR-ISx16 ISA "family" - embizone - 08-17-2014 It's just Logisim. Why do people keep capitalizing the 's'. Yes this is more relevant than the instruction set. RE: IizR-ISx16 ISA "family" - LordDecapo - 08-18-2014 Ya embi, that is so the most important part xD lol u need to get on skype, so we can talk about VLIW and the Belt, i want to use a speciallized system based on a paper i read from HP back in 1993, that describes an OOOexe kinda system in a VLIW, this allows it to accomidate to Cache missed better and other variably timed inst. As u can have variably timed Inst and the system doesnt get bogged down from stalls. makes compiling slightly easier to, u dont have to know hardware timing to make the VLIW program that way u only need to know the IS and have a way to find data depenedencies. RE: IizR-ISx16 ISA "family" - LordDecapo - 08-18-2014 Also embi, does ur belt u made in LogiSim have a scratch pad? RE: IizR-ISx16 ISA "family" - jxu - 08-19-2014 I'm impressed you used at least 12 colors in your scheme. RE: IizR-ISx16 ISA "family" - LordDecapo - 08-21-2014 (08-19-2014, 07:34 AM)͝ ͟ ͜ Wrote: I'm impressed you used at least 12 colors in your scheme.i have added 2 more colors since RE: IizR-ISx16 ISA "family" - Cutlassw30 - 08-23-2014 Learn verilog your neck-beard noobs but yeah looks "ight" RE: IizR-ISx16 ISA "family" - LordDecapo - 08-23-2014 ha cut, guess what?? screw you RE: IizR-ISx16 ISA "family" - Tjakka5 - 08-24-2014 I dont get it. Dayum |