05-16-2014, 09:12 AM
I've been working on a RiSC style 16 bit IS for use in my next CPU build. It's a modified version of Nickster's CSC-16. I am trying to decide what sort of instructions I should include in the 2 empty OP codes and also I'm looking for another branch condition to include. This IS is intended to run on a 16 bit CPU with potentially either Von Neumann or Modified Harvard architecture and I was wondering if there were any particular instructions that would be important to include. I would be grateful for any sugestions.
A: Write Reg
B: Read Reg 1
C: Read Reg 2
![[Image: PjIIvTc.png]](http://i.imgur.com/PjIIvTc.png)
RSAC stands for Reduced Stonechypher-Allen Computing (sorry Nickster if I misspelled that
)
A: Write Reg
B: Read Reg 1
C: Read Reg 2
![[Image: PjIIvTc.png]](http://i.imgur.com/PjIIvTc.png)
RSAC stands for Reduced Stonechypher-Allen Computing (sorry Nickster if I misspelled that
