Prepare your anus this instruction set is REALLY huge...
With a total of 62 OP codes and 24 registers and all in 16 bit with 1 cycle load from RAM!
I must post as a image because the text is too big :/
Registers, flags register bit layout, and instruction formats (only 2!):
![[Image: d3d2L2z.png]](http://i.imgur.com/d3d2L2z.png)
Operations (all 62 of them, note the order is Mnemonic -> Usage -> Register transfers -> instruction formats):
![[Image: SyxFrwO.png]](http://i.imgur.com/SyxFrwO.png)
On the assembly level she is pretty as well, I will get some programs in asm written out shortly...
Inspiration from:
X86 (the good x86 not the post i386 x86
) http://www.mindshare.com/files/ebooks/x8...ecture.pdf
MIPS https://www.student.cs.uwaterloo.ca/~isg...ps/opcodes
RiSC-16 http://www.ece.umd.edu/~blj/RiSC/RiSC-isa.pdf
My own knowledge
EDIT:
For my core layout I will choose a 2 stage pipelined dual processor design that intel used with 8086 and 8088 microprocessors. The two processors inside the core are:
BIU: Bus Interface Unit, runs on a much faster clock than the EU and has a 64 byte 8 long instruction queue inside to load instructions into while the EU is executing to take load of the system bus and have minimal amount of instruction wait.
EU: The guts of the CPU, this holds all the ALUs and some registers (besides addressing registers ofc). The EU can only go into a wait state under 3 conditions.
1: Data hazard, data needs to be fetched from main memory that is not in the instruction queue (which is always the case with memory operations). The EU must wait for main memory to respond to the request before resuming execution. This sends a interrupt to the BIU as well and well prevent any instruction prefetches while this is underway.
2: Jump past the instruction queue, this is the worst case as all instructions in the queue must be cleared out to prevent hazards. This creates bubbles in the instruction pipeline. (Branch prediction would be nice here...)
3: The one in which happens the least is the EU takes too long to execute and the BIU just sits there doing nothing (instruction queue is filled up.)
This is the block diagram of the 8086, mine will look quite same on the block level.
![[Image: image002.jpg]](http://www.cosc.brocku.ca/~bockusd/3p92/Local_Pages/8086_achitecture_files/image002.jpg)
-cutters
With a total of 62 OP codes and 24 registers and all in 16 bit with 1 cycle load from RAM!
I must post as a image because the text is too big :/
Registers, flags register bit layout, and instruction formats (only 2!):
Operations (all 62 of them, note the order is Mnemonic -> Usage -> Register transfers -> instruction formats):
On the assembly level she is pretty as well, I will get some programs in asm written out shortly...
Inspiration from:
X86 (the good x86 not the post i386 x86
) http://www.mindshare.com/files/ebooks/x8...ecture.pdfMIPS https://www.student.cs.uwaterloo.ca/~isg...ps/opcodes
RiSC-16 http://www.ece.umd.edu/~blj/RiSC/RiSC-isa.pdf
My own knowledge
EDIT:
For my core layout I will choose a 2 stage pipelined dual processor design that intel used with 8086 and 8088 microprocessors. The two processors inside the core are:
BIU: Bus Interface Unit, runs on a much faster clock than the EU and has a 64 byte 8 long instruction queue inside to load instructions into while the EU is executing to take load of the system bus and have minimal amount of instruction wait.
EU: The guts of the CPU, this holds all the ALUs and some registers (besides addressing registers ofc). The EU can only go into a wait state under 3 conditions.
1: Data hazard, data needs to be fetched from main memory that is not in the instruction queue (which is always the case with memory operations). The EU must wait for main memory to respond to the request before resuming execution. This sends a interrupt to the BIU as well and well prevent any instruction prefetches while this is underway.
2: Jump past the instruction queue, this is the worst case as all instructions in the queue must be cleared out to prevent hazards. This creates bubbles in the instruction pipeline. (Branch prediction would be nice here...)
3: The one in which happens the least is the EU takes too long to execute and the BIU just sits there doing nothing (instruction queue is filled up.)
This is the block diagram of the 8086, mine will look quite same on the block level.
-cutters
