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+---- Thread: R1600 Risc 16 bit instruction set. (/thread-1845.html)
R1600 Risc 16 bit instruction set. - Cutlassw30 - 01-04-2014
Prepare your anus this instruction set is REALLY huge...
With a total of 62 OP codes and 24 registers and all in 16 bit with 1 cycle load from RAM!
I must post as a image because the text is too big :/
Registers, flags register bit layout, and instruction formats (only 2!):
![[Image: d3d2L2z.png]](http://i.imgur.com/d3d2L2z.png)
Operations (all 62 of them, note the order is Mnemonic -> Usage -> Register transfers -> instruction formats):
![[Image: SyxFrwO.png]](http://i.imgur.com/SyxFrwO.png)
On the assembly level she is pretty as well, I will get some programs in asm written out shortly...
Inspiration from:
X86 (the good x86 not the post i386 x86
) http://www.mindshare.com/files/ebooks/x86%20Instruction%20Set%20Architecture.pdfMIPS https://www.student.cs.uwaterloo.ca/~isg/res/mips/opcodes
RiSC-16 http://www.ece.umd.edu/~blj/RiSC/RiSC-isa.pdf
My own knowledge
EDIT:
For my core layout I will choose a 2 stage pipelined dual processor design that intel used with 8086 and 8088 microprocessors. The two processors inside the core are:
BIU: Bus Interface Unit, runs on a much faster clock than the EU and has a 64 byte 8 long instruction queue inside to load instructions into while the EU is executing to take load of the system bus and have minimal amount of instruction wait.
EU: The guts of the CPU, this holds all the ALUs and some registers (besides addressing registers ofc). The EU can only go into a wait state under 3 conditions.
1: Data hazard, data needs to be fetched from main memory that is not in the instruction queue (which is always the case with memory operations). The EU must wait for main memory to respond to the request before resuming execution. This sends a interrupt to the BIU as well and well prevent any instruction prefetches while this is underway.
2: Jump past the instruction queue, this is the worst case as all instructions in the queue must be cleared out to prevent hazards. This creates bubbles in the instruction pipeline. (Branch prediction would be nice here...)
3: The one in which happens the least is the EU takes too long to execute and the BIU just sits there doing nothing (instruction queue is filled up.)
This is the block diagram of the 8086, mine will look quite same on the block level.
![[Image: image002.jpg]](http://www.cosc.brocku.ca/~bockusd/3p92/Local_Pages/8086_achitecture_files/image002.jpg)
-cutters
RE: My biggest and scariest instruction set ever. - Iceglade - 01-04-2014
* Iceglade runs
Also cut, your title is so long it's going to make replying annoying :p
RE: My biggest and scariest instruction set ever. - Cutlassw30 - 01-04-2014
(01-04-2014, 01:04 PM)Iceglade Wrote: * Iceglade runsFixed and updated.
Also cut, your title is so long it's going to make replying annoying :p
RE: R1600 Risc 16 bit instruction set. - Iceglade - 01-04-2014
Aha, thanks. Also, I might be completely wrong about this but how practical is native multiplication and division?
RE: R1600 Risc 16 bit instruction set. - Cutlassw30 - 01-04-2014
(01-04-2014, 02:38 PM)Iceglade Wrote: Aha, thanks. Also, I might be completely wrong about this but how practical is native multiplication and division?
Very, its almost needed to run larger programs. I have a asm extension to allow floating point and for that you at least need integer multiply/divide. And again a lot of programs multiply.
RE: R1600 Risc 16 bit instruction set. - himehowareu - 01-08-2014
Can i use this to write my OS (MCX) for your Redstone computer
If yes message me please and also could you sent me or post estimated times on the components
RE: R1600 Risc 16 bit instruction set. - Cutlassw30 - 01-09-2014
Yes you can use this. This IS would be impossible almost to make in MC however... (like 200 tick clock lol)
RE: R1600 Risc 16 bit instruction set. - EDevil - 01-09-2014
(01-09-2014, 01:07 PM)Cutlassw30 Wrote: Yes you can use this. This IS would be impossible almost to make in MC however... (like 200 tick clock lol)
Fairly reasonable.
RE: R1600 Risc 16 bit instruction set. - redstonewarrior - 01-09-2014
I moderately hate you. On a side note, you can get more CISC with this, and at one point, get to do some logically interesting things in the instruction decoding sections, including register renaming, memory fetch optimization, instruction reordering, and more. You'll need about 2 ORE builds worth of space for this. 256 may not be high enough for the overlapping busses.
Just kidding. It would be under a plot, but still monstrous and unusable. The instruction decoding logic would literally be the slowest part.
RE: R1600 Risc 16 bit instruction set. - Cutlassw30 - 01-09-2014
(01-09-2014, 04:42 PM)redstonewarrior Wrote: I moderately hate you. On a side note, you can get more CISC with this, and at one point, get to do some logically interesting things in the instruction decoding sections, including register renaming, memory fetch optimization, instruction reordering, and more. You'll need about 2 ORE builds worth of space for this. 256 may not be high enough for the overlapping busses.
Just kidding. It would be under a plot, but still monstrous and unusable. The instruction decoding logic would literally be the slowest part.
CISC sucks.
This is more RISC than ARM is...
RE: R1600 Risc 16 bit instruction set. - redstonewarrior - 01-09-2014
Wording failure, I meant you could bring this into the world of CISC.
RE: R1600 Risc 16 bit instruction set. - Cutlassw30 - 01-09-2014
(01-09-2014, 09:53 PM)redstonewarrior Wrote: Wording failure, I meant you could bring this into the world of CISC.
but CISC sucks
Also I would say the code is more dense on the byte level for RISC than CISC.
RE: R1600 Risc 16 bit instruction set. - WrytXander - 01-09-2014
*Sees there are only two formats*
Looks at his 8 bit RiSC mod, 3 formats.
FUUUUUUUUuuuUu