Application from Quebec !

[MrBiron]

I everyone !
I want to submit to you my application for your building server !
There is the form:
Minecraft name:amnesio42

What do you like the most about redstone?: Analogy with real semi-conductor, and it's potential

What's a thing you have made which demonstrates redstone knowledge?: Compact divider, multiplier, scoreboard system (as used in Cray CDC 6600), a compact dual channel ram desing

What do you plan on making for your build trial?: All does you want lol, seriously i'm already planning to build a CISC CPU, I've made all my component needed, and now i'm at the step to get ir to work all together

Do you agree with the rules?: Of course !




I build several redstone component intended to be mounted in serial and sharing instruction and data bus, like 16 bit compact divider (47L x 42W x 17H blocks) which use shifting register and a conditional subtractor to perform the math itself, and a counter connected to a clock to make it does all cycle needed (16 * 64 tick cycle)

 
. I also build a compact 16 bit multiplication unit (I don<t know the appropriate word, I`m a French-Canadian) which is also pretty compact (29L x 42W x 17H block)

 

 These executions units are build to be independent, once operand are loaded, input don`t ned to be kept, allowing to use the input bus to load operand to another executions units. They also have all their own timing, that`s why  i also build a semaphore based memory access system, preventing two execution units to send data to memory at the same time, while using the same memory bus available for all executions units.


There is 2 Division execution units and 2 multiplications units connected in serial, other instruction will be added (like bit shift, with up, down and rotate, add, subtract, increments, logic test etc). as division take a lot of time, there is two, switching to the other after one is started, same thing applies in the scoreboard to keep track if the requested unit is available)



 
I Also worked on a scoreboard system to allow better utilisation of executions units, testing at the decoding of an instruction if the output of a previous instruction is needed to perform next instruction and if ti has been writen, and also another scoreboard to test if the execution units needed to perform it is free. If both condition are ok (don`t require awaited output, and the instruction requiered is free) the clock signal will be the sent to the pipeline.


when there is a conflict (testing address 0 on both green and yellow channel, to a adress 0 awaiting to be freed (black)) it output a signal that is used to block the clock signal) see the redstone lamp




When adress 0 is free (black) there is no conflick when testing adress 0 on green and yellow

Now no signal blocking the clock to geet to the instruction decoding pipeline !
This allow instruction level parallelism.
I Also developed a dual channel ram module, that allow to read two different (or the same) address at the same time, to be connected with the imput channel of an alu or a execution unit. There is also 2 independent writing channel, one can be used to recieve data from execution units, and another to anything else



I Think I can be a productive member of your community, and bring a lot of new idea or solution to a lot of probleme!


Contact me for question, or to see it on my personnal server !

[LambdaPI]

Application and pictures look very nice, but you have to specify what you want to build for the trial

Would you be comfortable with an ALU or a multiplier?

[MrBiron]

Application and pictures look very nice, but you have to specify what you want to build for the trial

Would you be comfortable with an ALU or a multiplier?

Yes i will be, I already build a multiplier as I said, and it work with two shifting register and a conditional adder, instead of a simple array of  conditional adder with wired shifter. It's really compact. I'm also comfortable with making division (and also modulo, of course)
For trial I can make an ALU, a divider or a multiplier, to you're choice. 

I've also made a memory acces manager, that use "flag" system to handle ramdom write acces demand to memory from differents sources (differently clocked execution units, as an example) Very usefull to handle a lot of random imput while keeping memory coherent.

My goal is to integrate an array of independant executions units, sharing the same memory. As in 60' computer, memory is far faster than the cpu core, make it waste a lot of "time" waiting, so as in the Cray CDC 6600 or the more recent IBM CELL, making a central cpu core, fast, that only manage some independent executions units, by feeding them and monitoring RAW condition and disponibility of a "module" for executing the instruction.

[LambdaPI]

If you are able to build the ALU/divider/multiplier from memory and explain it very well, then I will accept you for the trial.

Just come on the server whenever you have time and ask for a trial. Sometimes there will be noone to give it to you, but at some point someone will trial you.

Good Luck