Links: Specification (GDocs), Mapping (GSheets)
The title sums it up well. I'm going to be working on a new architecture / instruction set and building a CPU to go along with it. It's just a warmup exercise for some of the cooler stuff I'm planning for later :3.
Ideas so far:
Updates:
The title sums it up well. I'm going to be working on a new architecture / instruction set and building a CPU to go along with it. It's just a warmup exercise for some of the cooler stuff I'm planning for later :3.
Ideas so far:
- Harvard memory architecture
- 4 bit data width; 8 bit instruction width
- 3 general purpose registers and one null register (might substitute for a 4th GPR)
- 16 lines of instruction memory
- No higher level storage 8 16 words of secondary data storage
- No call stacks - not practical for such a small instruction space
- 2 or 3 stage pipeline - a new thing I haven't done yet
- Conditional branching with some simple conditions (zero/overflow flags)
- Branch prediction
Updates:
- 2016-09-12: I have made an official for mapping of the instruction set. Please check it out and make comments here!
- 2016-09-13: I have added two new instructions, Load and Store, both of which take up the rest of the empty instruction space. They accept 3 bit memory addresses which are separate from the register address space, so it adds an extra 8 words of data capacity.
- 2016-09-13: I have added a new document, the architecture specification. This will be the home of all the specs that fit better in a typed document than a table.
- 2016-09-16: A rough wiring diagram has been drawn; now working on digitizing it and figuring out tick speeds for components.
- 2016-11-15: I got distracted by school and some other projects, I'm going to start working on this again.
I'M BAAAAAAACK!