07-23-2013, 08:14 AM
(07-07-2013, 01:30 AM)CMOSprinkles Wrote: I'm using the typical Von Neumann architecture for this at the moment. I suppose that could change if I run into issues with the bottleneck, though I think that 10 ticks should be a reasonable goal even for a Von Neumann computer. As for the interactive element, I'm still working on how to support that. It will have something to do with the GPU's hit detection and it may involve a flag register. As for the memory; the CPU will have 4 General Registers as well as an 8 byte stack. The main memory will be expandable, instant wiring will make expansion simple, and I will look into memory mapped I/O as soon as I get the chance. The Program Memory will also be expandable in the same way. How many bytes of each I put in will depend on what I need for my programs, but I will probably start with something like 64 bytes of each. I will be using the swapping technique to save space in the main memory. These are just some of my goals with this computer, but it is still a long way from being finished. I'm still debating using a RISC instruction set.Thanks good luck with 1 hertz,
Hey Bill, your post must have sneaked in there, I didn't see it before. I would be happy to help with SAC or SAC 2! I may not have any solid designs for hardware components yet, but I am always willing to help with designing the architecture. If speed is your goal, I can tell you how fast each component needs to be, and I'm sure I can assist if you need help making any of the components function more quickly.
Also I have slowed production on SAC and SAC videos due to
Stufz but I can help on this if you need anything done.
Also I recommend asking Craftriot about OISC, he is developing
It to help MC computers to advanced to the next speed.