03-31-2015, 10:24 PM
(This post was last modified: 03-31-2015, 10:31 PM by LordDecapo.)
So guys, i finally am officially posting stats for IizR14. i have solidified most of these to be final. Only a couple things here and there are subject to change.
-6tick clock (goes to 8 during serial transmissions, since I use 1tick/bit serial)
-6 stage pipeline
-128bytes of RAM(runs via Bytes and 8byte Pages so it can be connected to external storage)
-16-32 byte L1 cache (depending on ticks required)
-32memory mapped locations
-software and hardware based interrupt and exception support
-7 serial hardware ports (16bit sub addressing supported) with 1 being keyboard, 2 being network and 3 being display, so 4 universal ports.. all with interrupt support.
-8bit data width
-256lines of PROM
-64byte Instruction Cache (for external Inst. memory)
-16bit external Instruction addressing support with full Call and Return support.
-19bit external Data storage support (16bit page addressing, each page has 3 bit sub address delt with after a page is in RAM)
-And some more stuff I probably forgot to put in
The IS so far is this:
![[Image: ASg6E0U.png]](http://i.imgur.com/ASg6E0U.png)
The IS has some stuff that needs addressing and is subject to change, but this is it so far.
As i am closer to completion then ever, i will be making paperwork for this CPU on how it functions, how the individual ops will flow through the pipeline, and how the kernel/PROM will arranged. As the PROM will be used for built in functions that u can call to from a program stored externally.
so ya
here it is, xD
-6tick clock (goes to 8 during serial transmissions, since I use 1tick/bit serial)
-6 stage pipeline
-128bytes of RAM(runs via Bytes and 8byte Pages so it can be connected to external storage)
-16-32 byte L1 cache (depending on ticks required)
-32memory mapped locations
-software and hardware based interrupt and exception support
-7 serial hardware ports (16bit sub addressing supported) with 1 being keyboard, 2 being network and 3 being display, so 4 universal ports.. all with interrupt support.
-8bit data width
-256lines of PROM
-64byte Instruction Cache (for external Inst. memory)
-16bit external Instruction addressing support with full Call and Return support.
-19bit external Data storage support (16bit page addressing, each page has 3 bit sub address delt with after a page is in RAM)
-And some more stuff I probably forgot to put in
The IS so far is this:
The IS has some stuff that needs addressing and is subject to change, but this is it so far.
As i am closer to completion then ever, i will be making paperwork for this CPU on how it functions, how the individual ops will flow through the pipeline, and how the kernel/PROM will arranged. As the PROM will be used for built in functions that u can call to from a program stored externally.
so ya
here it is, xD