03-03-2015, 04:18 AM
(This post was last modified: 05-24-2017, 12:06 PM by Magic :^).
Edit Reason: Delet ":3"
)
UPDATE:
.. well a late update really.
me and embi made a 4 tick 4 wide CCA a good while ago, and have been messing around with it for a while. It has a signal strength problem where in some cases it only outputs 1 signal strength
However!
I have designed a 4 tick 5 wide CCA which has 4 signal strength output worst case, and has the possibility of being expanded to be able to perform 4 tick 9bit calculations?!
idek anymore xD
I'm using this design in my new dataloop for my new CPU.
The aluified design has many possibilities too, like a feasible 7 tick accumulator based dataloop.
(you could go for 6 if you wanted a headache)
no pics because i'm sleepy. You can find the newest design at ./warp cca
.. well a late update really.
me and embi made a 4 tick 4 wide CCA a good while ago, and have been messing around with it for a while. It has a signal strength problem where in some cases it only outputs 1 signal strength
However!
I have designed a 4 tick 5 wide CCA which has 4 signal strength output worst case, and has the possibility of being expanded to be able to perform 4 tick 9bit calculations?!
idek anymore xD
I'm using this design in my new dataloop for my new CPU.
The aluified design has many possibilities too, like a feasible 7 tick accumulator based dataloop.
(you could go for 6 if you wanted a headache)
no pics because i'm sleepy. You can find the newest design at ./warp cca