I've made a logisim circuit of the adder's design. It shows how much stuff is compressed by the comparators quite (horribly) well 
Adder cell:
![[Image: lMkEB0n.png]](http://i.imgur.com/lMkEB0n.png)
Carry logic:
![[Image: YvjQsAD.png]](http://i.imgur.com/YvjQsAD.png)
notice how it is ORing together the relevant weighted cancel wires before cancelling weighted generates
there's a .circ file in the .zip attached here
(admins plz allow .circ attachments)
Adder cell:
Carry logic:
notice how it is ORing together the relevant weighted cancel wires before cancelling weighted generates
there's a .circ file in the .zip attached here
(admins plz allow .circ attachments)