My asynchronous pipelined CPU, aka AsPipe

[Magic :^)]

I have the dataloop stage running now, I've tested most of the ops. I don't have any prom to plug in yet though, so the most i can do is loop one instruction. Namely: a=a+1

I wrote out the Fibonacci sequence in the meantime though:

Code:

#initial reg loads, calculate first 2 terms
0000|   const
0001|   00000000
0010|   const
0011|   00000001
0100|   add 001
0101|   regread 001
0110|   add 010

#main loop
0111|   regread 001
1000|   regread 010
1001|   add 001
1010|   regread 010
1011|   regread 001
1100|   add 010

1101|   jump
1110|   00000111