Here, I'll give you some of the relevant stuff I've looked up that will give you an idea of how the system will work:
I'm using a buffered asynchronous pipeline: http://en.wikipedia.org/wiki/Pipeline_(computing)#Implementations
A document that discusses the handshake protocols (Mine are MC optimized, not exactly the same):
http://www.cs.columbia.edu/~nowick/nowick-singh-ieee-dt-11-published.pdf
Here's another wikipiedia heading specifically on Asynchronous CPUs:
http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU
My processor will be along the lines of what is described there.
By the way, these were looked up post-inception of this idea, I basically learned the terminology from there more than anything else, and helped me make some small improvements to my original designs.
EDIT: Yeah, I used to use terms like 'self-governing queue' and other random terms. No-one understood me DX
I'm using a buffered asynchronous pipeline: http://en.wikipedia.org/wiki/Pipeline_(computing)#Implementations
A document that discusses the handshake protocols (Mine are MC optimized, not exactly the same):
http://www.cs.columbia.edu/~nowick/nowick-singh-ieee-dt-11-published.pdf
Here's another wikipiedia heading specifically on Asynchronous CPUs:
http://en.wikipedia.org/wiki/Asynchronous_circuit#Asynchronous_CPU
My processor will be along the lines of what is described there.
By the way, these were looked up post-inception of this idea, I basically learned the terminology from there more than anything else, and helped me make some small improvements to my original designs.
EDIT: Yeah, I used to use terms like 'self-governing queue' and other random terms. No-one understood me DX