My asynchronous pipelined CPU, aka AsPipe

[Magic :^)]

Theoretically (again, one of my thought expiriments), one should be able to make a pipelined CPU where each clock cycle is actually triggered by the incoming program data, meaning it can run as fast as the data comes in. Thus, a clock is not needed, and it is therefore asynchronous.

Honestly, this sounds easier to build.

That's exactly how I'm implementing it! Program data moves through the stages until the correct one is reached, and when the instruction resolves, the data is deleted and allows more instructions to fill the space left behind. In practice, that's a handshake protocol that requests and passes data along the pipeline as needed.