01-14-2014, 11:38 PM
(01-14-2014, 02:22 PM)Cutlassw30 Wrote:(01-14-2014, 01:35 PM)Null Wrote:(01-14-2014, 09:38 AM)EvilDevil59NL Wrote: Where did you find ripple carry adders in this post?
And if he did use them, its probably because #swag
I Sneaked Into His Plot And Found Them In That Computer...
Now I Just Need To Reverse Engineer It... Nya Nya Nya...
Still better architecture than ive seen anyone else make. Who gives a flying fuck about implementation the guy is smart. But thats why I sorta dislike this server, everyone only cares about how good something looks and how compact/fast it looks. No one cares about architecture.
And even with a 70 tick clock speed and not compact what so ever. Im going to call this the best computer on the server.
Ok cut I was explaining this on the server but you had to leave so I can tell you now.
Basicly the clock is a 7 second clock, each clock cycle does 1 step of the stepper. But an instruction like add takes more then 1 step to complete.
Example:
1st step - load value B into the TEMP register
2nd step - load value a into the alu and the temp reg into the alu and add them together
3rd step - save the result into another register
As there is only 1 bus every command must be executed like this, in a series of steps. In each step any register can be read from and saved to but as there is only 1 bus you can only do 1 register at a time, get it?
But, as we want to access the next location in ram to get the next instruction after the current add instruction is finished we want to do a little addition. Now this takes another 3 steps. There is also one final step that resets the stepper back to step 1. In total that = 7 steps every instruction will need to do no matter what it is. So it takes 7 clock cycles to complete one instruction cycle. I know this is very slow but as its von neumann it needs to be like this.