12-20-2015, 08:15 AM
I've been working recently on a hard disk drive in minecraft that would be of use in large computers that need ludicrous amounts of storage (from 1 byte to however many you want to address with a data density that approaches 2bits/block with increasing size). I don't have photos at the moment, but I just got off of school for the break and I'm working towards my first functional test. The basic premise I borrowed from Koala_steamed. An analog signal is looped around infinitely on a loop of redstone comparators that preserve its value. This loop has a start/end point that can be interrupted by moving a block with a sticky piston to erase a byte (2*4-tick pulse = 8 bytes) and likewise the output at that same point is piped into an ADC that can pulse some D Flip-Flops to convert each 4-tick pulse into two latched quartets. Of course writing on this also means I'd need a DAC that synthesizes two 4-tick pulses, which I've also already made. Currently I'm missing the control unit. This would tie everything together. With some inputs/outputs (X ADDR, 8 DATAI, 8 DATAO, 2 OPCODE, 1 DONEPULSE), this unit would count what byte the disk is currently reading/writing and compare that to the ADDR input. The opcodes are as follows. (00-READ,01-WRITE,1X-NOP) The DATAI and DATAO are seperate because they are directly tied to the DAC and ADC, respectively, and don't actually interact with the control unit. For interacting with a computer, those would need to be combined into a bidirectional bus so some multiplexed addressing could set and read the data values depending on whether a write or read is occuring. When the ADDR is equal to the count, the OPCODE decides which mechanism to engage and the DONEPULSE pin is pulsed. Some latches could make this entirely visible to a computer as 4 registers. ADDR, DATA, OP and DONE. That is, assuming one wanted 256 bytes on this hard disk drive. Fortunately, the only part that needs scaling is the counter and it's jumbled however-many-input AND gates. Unfortunately, every read/write cycle takes an entire rotation to work, so a 256 byte HDD would take 25.6 seconds to read/write. The logical thing after that is to multiplex 4 512-byte or 8 256-byte platters to make a 12-bit addressable HDD. This, paired with a von neumann arch CPU could entirely store dozens of large programs, eliminating the need to large ROM structures for programming. Instead, two ROM programs would be required. A LOAD X program and a WRITE INPUT program. Load X would require a program length and starting address and it would load that into RAM and execute it. The other would wait for input on a register with switches and a latch or something and would write the hard disk drive until the computer were powered down and refreshed.
Sorry if this is a lot of text with no pictures, but at the moment the closest I have to a working model is a device that writes 1111111100000000 to the drive and can clear the immediate set of 11111111.
If you have something Von Neumann style that you wouldn't mind helping me around, I'd love to hook this up to it. Instruction sets would also be appreciated, because I know some require 16-bytes per instruction and require all 16-bytes to be retrieved at once, but a 2-byte/address could also be arranged.
Sorry if this is a lot of text with no pictures, but at the moment the closest I have to a working model is a device that writes 1111111100000000 to the drive and can clear the immediate set of 11111111.
If you have something Von Neumann style that you wouldn't mind helping me around, I'd love to hook this up to it. Instruction sets would also be appreciated, because I know some require 16-bytes per instruction and require all 16-bytes to be retrieved at once, but a 2-byte/address could also be arranged.