A basic FPGA

[Tommyand]

Since I actually have a project now, I may as well post about it. On my school plot, (my username now being Kitlith,) I'm working on making a FPGA slice based on the one here: http://blog.notdot.net/2012/10/Build-your-own-FPGA

Old post can be found below:

What I've gotten done so far is the LUT, and the sync/desync logic. I'm working on the busses that will be tiled, (and must be able to transfer data in both directions,) and connecting them to the inputs and outputs.

What still needs to be done:

• Hook up outputs from the LUT. (This should be done now, and for the moment, whether or not the slice is driving a line will be determined by breaking/placing a piece of redstone...  Simplicity! (Or using a piston to block signal. (Or a comperator...) Configurability!))
  
• Hook up inputs to the LUT. ( Should also be almost done with this, but the one lest is a tricky one. May need to rebuild parts to get it in...   ) That was tricky. This will need refining before trial...  
  
• Verify that the bus, when tiled (stacked) will still be able to travel the distance. Good here. Requires some weird stacking configuration in one direction, but otherwise fine.
  
• Figure out how to hook a clock up, and such. This may require an additional (one-way!) bus carrying the clock signal. (This is where I am, along w/ below: )
  
• Testing a finished slice.
  
• Testing tiled (stacked) slices together, with different configurations depending on the slice.
  
• Do my Trial... 
  

So, I'm thinking that all configuration decisions besides the LUT will be exactly where the thingys are. That is, until I decide that I do want this programmable over serial, when it'll need to be configured through a series of shift registers, or other device to store data coming in over serial.

EDIT: I realized that, as it is right now, it is way too messy to use, or really build for a trial. I suppose... I could figure it out again while doing the trial. But it won't be very good/understandable. Not unless I figure out a good way to hook it all up, first. I'm working on remaking what I have so far, but it 's gonna be flatter, and color coded this time. And hopefully easier to look at and build. I have a Lookup Table built; unfortunately, I got interested in making a larger one, so I'll need to knock down the extra bits. 

I finally have something that works!
Shoutout to very_awesome_guy for stacking it for testing!

Pictures!

It's a pain to program, with the config everywhere, and having to do everything manually, but that's where v3 will come in! *facepalms*

I've made a Lookup Table that you can shift it's program in, so far, but I think I really want WE before I do much more. Look out trial, here I come!

---

So, I passed my trial. And now I'm on build.

I expanded the concept a little bit. The lookup table now takes 4 inputs gives 4 outputs. This means that each side of the slice can have an input and an output. Here are some pictures of this expanded FPGA:

However, earlier, I mentioned a LUT where you can shift the program in. I've been working on that lately, and... well... I had a few variants before I settled (with some help) on what I'm currently using. They mainly differ on how I'm disabling output when a line isn't selected.

The first two prototypes had the same idea, but one followed from the other. The main problem was getting these to not interfere with the shift register.

The first prototype worked better then the second, though the second would have been faster... if only I could reach all of the comparators. At this point, amh(some numbers), also known as Burrito, took a look, and... made it simpler and faster. Just look at the images:

But... that was only actually 3x4. So, I expanded it, and have been working on completing it. Here goes.

Not done. Totally not done. In fact, I dread finishing it. Still not sure how I'm going to get the serial line to all of the control points (pink wool). I'll worry about that later. For now, here's what's up.

• Absolutely no pistons. None. All of the (de-)multiplexers are bade with torches.
  
• Unfinished. The inputs are hooked up, but the outputs are not.
  
• Messy. I don't even want to think about that busing...
  
• Slow. This is impractical. However... how is a CPU in Minecraft practical?
  
• Programable! Each slice will take ~80 bits of information, 4 bits for each possible input (16), and 16(?) control lines.
  

The full album of pictures can be found here: http://imgur.com/a/bmnmX

Can I even say any more? I'm probably going to take a break from this. Crazy brought up OISC stuff, so I'm getting interested in making a subleq CPU again. We'll see what happens.

[LordDecapo]

Awesome! Hope this works out well
good luck!!
u may want to try and get on build first, then u will have more room + WE

[Tommyand]

Awesome!  Hope this works out well
good luck!!
u may want to try and get on build first, then u will have more room + WE

Well, yes. The plan is to build a stackable slice, get someone to come over and stack it for me, (and possibly copy it to another location over/under plow floor,) and then test everything together. However, I'm planning for this to be my build for my trial, I'm just figuring it out and letting people know. So, I'm not going to wait to do a working version, but I will wait to refine it, if I'm still interested in it.

[LordDecapo]

Cool cool! A good fPGA will definitely pass a trial. Let me know u r progress, I'd love to see it

[Tommyand]

Cool cool! A good fPGA will definitely pass a trial. Let me know u r progress, I'd love to see it

So... I'm not sure why it took so long for me to realize that could be driving input and output from either side... So, that'll hopefully make it less messy. I'm taking my time, and I'm labeling everything. I'm color coding as much as I can think of. So... refining! xD

[Tommyand]

I made a working version! But I'm still not done.

Yes, this is essentially a bump, because editing doesn't bump...

[Noah7545]

Im interested to see how this works out. Maybe you could build a cpu in the FPGA when you are finished.

[Tommyand]

Im interested to see how this works out. Maybe you could build a cpu in the FPGA when you are finished.

I'd love to build a CPU with one of my working prototypes. Though... I have the sinking feeling that it would be waaaaay bigger than the BFCPU... So many slices... xD

I also don't know enough about using FPGAs to do it, I'd have to find someone experienced enough that didn't mind doing it manually... without any real tools... ._.

[Tommyand]

Another bump. Title post change. Appearantly the maximum number of images per post is 15, so there's two extra in the imgur album.

[LambdaPI]

Wow. I didn't know i contributed.
Lol (I iz da very_awesome_guy)


Pretty cool stuff tho

[Tommyand]

Wow. I didn't know i contributed.
Lol (I iz da very_awesome_guy)


Pretty cool stuff tho

Heh. You stacked it for me while I was still a student. Of course that was a contribution.

[newomaster]

Really awesome! This is the first time I've seen an FPGA in MC (that I remember, anyway). Keep up the good work!

[Tommyand]

Really awesome! This is the first time I've seen an FPGA in MC (that I remember, anyway). Keep up the good work!

Well, I know it's not the first. I remember seeing some engineering student's FPGA, but I think that was more monolithic? And there are probably others, too.