FIFO Memory

[GISED_Link]

Queue Memory

Heeeeeeello !

A FIFO is a memory that addressed for you the datas in FIFO order (First In First Out). You can easilly earase the last input, go 1 step farwad and reset all the memory.

[video=youtube]http://youtu.be/HB8YHf-ggro[/video]

Minecrfat version : 1.2 - 1.8 and higher

[en]
There is a FIFO memory (first in first out). You can save 8 bits of data and they will be automatically addressed.

Features :

• automatic save (rising edge of the CLK)
  
• fast data save rate, max 1.2 Hz
  
• The last slot is protected for overwriting
  
• All the usefull command
  • reset all the slots
    
  • one step farwad
    
  • reset the last input
    

We can use it for :
- save the measurements
- Plug and play memory
- control the data bus

Contact me if you need more bits wide.

[spoiler=screenshots]

Front view


Command signals


Right view


Output view


Top view
[/spoiler]

[greatgamer34]

AKA a stack IIRC

there are much more compact versions of a stack, but nicely done!

[MelvinS4_]

AKA a stack IIRC

there are much more compact versions of a stack, but nicely done!

Stacks are LIFO, queues are FIFO.

[GISED_Link]

Do you agree with that ?

If yes, my memory is a queue.

[LordDecapo]

^^
Lol nice GG

[Magic :^)]

Nice, queues are pretty handy. I've even used them for pipelining.

EDIT:
I watched the video, I love the music XD
From what I could see from the video, our queues work in a similar way :3
Mine uses an SR latch at each word. The latch feeds back and resets itself if there is an empty latch in front.
The output of the SR was connected to repeater lock memory, but idk if you used those
\-_^/ <-(That's a shrug)
I really want to take a look at it later :3

[GISED_Link]

The music : Yazoo - Don't Go ( Class X Re-mix )
https://www.youtube.com/watch?v=54AFmwSSqbc

"Mine uses an SR latch at each word. The latch feeds back and resets itself if there is an empty latch in front."

Mine, too. But the dectection of the empty space is managed by the hidden 9th bit (on the right). So it's easy to add some bits (by example for a 16 bit version).

But I have added a propagation control, so the signal will not go through the next memory if this one is not empty. So the RS can easily retain the value (so, no needing of the reapeter lock).

[tokumei]

I have a different concept for FIFO memory. It involves a read pointer amd a write pointer.

When you push data, it saves it to the memory at the pointer, then increment the pointer by 1 (overflows at the last address of the queue). I haven't developed any logic for if the queue is full yet, but you can probably easily do so using the existing circuitry involved with the read conditions.

When you pop data, it involves a bit of conditional logic. If the read pointer isn't the same as the write pointer, then read the data at the pointer and increment by 1 (same pointer overflow as above). If it is the same, then some other action must be taken (return zero, or maybe save a 1 to a flag register) and it does NOT increment the pointer.

I have made a hardware implementation of this concept that works with virtually any memory system with read/write functions. It involves a couple of shift registers connected into themselves for the pointers, where each individual output is connected to a read or write trigger on a memory cell. There'so also a bit of logical circuits (mainly AND gates) connected between the two shift registers for preventing reading from an empty queue.

[greatgamer34]

i failded hard ;-;

sorry gais