Yo, it's Capo 
How it going 'er-body!
So as some have you may know I have been consistently working on the same ever evolving CPU architecture design for quite some time.
It's gone through many stages.
-All control wires in one place kinda IS,,,
-Then a super shit wannabe-RISC
-Then to a RISC
-Then added OOOexe (Out of Order Execution)
-Then made to a CISC hyperthreaded Superscalar OOOexe
-Then scraped OOOexe
-Then scraped Superscalar
-Then scraped the HyperThreading
(Note the scraping was cause of gay as hell torch glitches)
-Finally settled on a parellelized CISC
And that is where it is currently and will stay for this iteration, may change to a Belt Arch. On my next LogiSim rendition... But that is for another post.
This one is about my current MC implementation.
I wanted to post this as an Update,
You can warp to the CPU with /warp IizRCPU
Last night I reached a good milestone (IMO) that I can now manually clock the CPU (everything except the PC, so u have to input ur Inst or at a time currently) and run most of the Mode1 operations.
So far only 1 bug, which was a known one, I just have to time the Writeback pulse.
I will keep updating this post with current status of the CPU as well as post the Is here for you all to see after I get off work.
Current NEEDED ToDo:
-Mode0 and related hard coding in the CU as well as Mode0 Related buffers (only 2 buffers need to be installed)
-Branch Unit/PC controller
-Clock
-Debug/Timing verification.
Nonessential ToDo:
-Finish RAM
-Add IO/UI interface
Those shouldn't take too long, but I work a lot so I'm not making any promises on a completion date.
Hopefully will have the Clock, and Branch unit done tonight, just leaving the Mode0 and final debug
UPDATE: Also I'm proud to say that I have debugged about 3/4 of my Mode1 operations. And just got unconditional branching set up. It has a couple timing bugs tthat need to be worked out for it to run on the 10tick clock. But it runs Direct, Calculative Positive (adding to PC), and Calculative Negative (subtract from PC ) unconditionally perfectly on a manual clock.
Will bbe timing that tonight as well as trying to hook up my conditionals and Call/Return.
Wish me luck :]
How it going 'er-body!
So as some have you may know I have been consistently working on the same ever evolving CPU architecture design for quite some time.
It's gone through many stages.
-All control wires in one place kinda IS,,,
-Then a super shit wannabe-RISC
-Then to a RISC
-Then added OOOexe (Out of Order Execution)
-Then made to a CISC hyperthreaded Superscalar OOOexe
-Then scraped OOOexe
-Then scraped Superscalar
-Then scraped the HyperThreading
(Note the scraping was cause of gay as hell torch glitches)
-Finally settled on a parellelized CISC
And that is where it is currently and will stay for this iteration, may change to a Belt Arch. On my next LogiSim rendition... But that is for another post.
This one is about my current MC implementation.
I wanted to post this as an Update,
You can warp to the CPU with /warp IizRCPU
Last night I reached a good milestone (IMO) that I can now manually clock the CPU (everything except the PC, so u have to input ur Inst or at a time currently) and run most of the Mode1 operations.
So far only 1 bug, which was a known one, I just have to time the Writeback pulse.
I will keep updating this post with current status of the CPU as well as post the Is here for you all to see after I get off work.
Current NEEDED ToDo:
-Mode0 and related hard coding in the CU as well as Mode0 Related buffers (only 2 buffers need to be installed)
-Branch Unit/PC controller
-Clock
-Debug/Timing verification.
Nonessential ToDo:
-Finish RAM
-Add IO/UI interface
Those shouldn't take too long, but I work a lot so I'm not making any promises on a completion date.
Hopefully will have the Clock, and Branch unit done tonight, just leaving the Mode0 and final debug
UPDATE: Also I'm proud to say that I have debugged about 3/4 of my Mode1 operations. And just got unconditional branching set up. It has a couple timing bugs tthat need to be worked out for it to run on the 10tick clock. But it runs Direct, Calculative Positive (adding to PC), and Calculative Negative (subtract from PC ) unconditionally perfectly on a manual clock.
Will bbe timing that tonight as well as trying to hook up my conditionals and Call/Return.
Wish me luck :]
