01-25-2020, 08:12 AM
(This post was last modified: 01-31-2020, 11:20 AM by Endershadow.)
I've tried designing a CPU multiple times but I always ran into some issue with implementing the instruction set. I finally (after many years of on-off design) have come up with a design that's mostly finalized. The only thing left to implement is about half of the processor control unit. I've attached the current version of the ISA, but I'll give a rundown of it in this post anyway.
SRIS-16 (Simple RISC Instruction Set) is a 16 bit CPU. The memory bus, registers, and memory addressability are all 16 bit (hence the 16 in the name).
It has 16 registers. Register 0 is the null register and is hardwired to null. The remaining 15 registers are general purpose and can be used for anything.
It has 35 instructions which are detailed in the attached text file.
One of the nice features about this is that it can execute all instructions in a single clock cycle. The only possible exception to this would be the memory instructions, but that's entirely implementation specific. Another nice thing is that you load 16 bit constants into the registers as well as do relative jumps with 16 bit constants all while staying within 16 bit instructions. The way I accomplished this is by having an internal 8 bit register which stores the upper 8 bits of the constant and a dedicated instruction for setting it with an 8 bit constant. This 8 bit register is part of the flags register and so pushing/popping flag data onto/off of the stack also affects it. The lower 8 bits of the constant are encoded into the instruction as well as a bit which specifies whether to sign extend the lower 8 bits or use the special register as the upper 8 bits.
While there is currently no stack pointer for stack operations since it uses specialized stack memory, a future revision might allow for using normal memory for the stack.
Here is a color coded visualization of the instruction set
SRIS-16 (Simple RISC Instruction Set) is a 16 bit CPU. The memory bus, registers, and memory addressability are all 16 bit (hence the 16 in the name).
It has 16 registers. Register 0 is the null register and is hardwired to null. The remaining 15 registers are general purpose and can be used for anything.
It has 35 instructions which are detailed in the attached text file.
One of the nice features about this is that it can execute all instructions in a single clock cycle. The only possible exception to this would be the memory instructions, but that's entirely implementation specific. Another nice thing is that you load 16 bit constants into the registers as well as do relative jumps with 16 bit constants all while staying within 16 bit instructions. The way I accomplished this is by having an internal 8 bit register which stores the upper 8 bits of the constant and a dedicated instruction for setting it with an 8 bit constant. This 8 bit register is part of the flags register and so pushing/popping flag data onto/off of the stack also affects it. The lower 8 bits of the constant are encoded into the instruction as well as a bit which specifies whether to sign extend the lower 8 bits or use the special register as the upper 8 bits.
While there is currently no stack pointer for stack operations since it uses specialized stack memory, a future revision might allow for using normal memory for the stack.
Here is a color coded visualization of the instruction set