Overflow detection

[Magic :^)]

https://www.cs.umd.edu/class/sum2003/cms...rflow.html

This page explains it extremely well.
An easy-to-understand way to check for overflow is to check if the MSb's of the inputs are equal, and then see if the output MSb is different.

on the linked page, UB stands for unsigned binary and 2C stands for 2's complement. On ORE, we usually just refer to Cout when talking about UB overflow btw.

[PNWMan]

Basically:

• 2's complement overflow occurs if adding 2 similarly signed numbers results in a different sign.
  
•  To detect overflow, see if the XOR of the Couts of the 2 MSBs is 1.
  
• Overflow will never occur when adding 2 differently signed numbers.
  
• This type of overflow is different from just the Cout.
  

[GISED_Link]

Basically:

• 2's complement overflow occurs if adding 2 similarly signed numbers results in a different sign.
  
•  To detect overflow, see if the XOR of the Couts of the 2 MSBs is 1.
  
• Overflow will never occur when adding 2 differently signed numbers.
  
• This type of overflow is different from just the Cout.
  

If we go a bit further with those flags :



With 8 bit register


I don't really understand why in the last addition the falg N is set ...

source : https://paws.kettering.edu/~jkwon/teachi...umbers.pdf

[Koyarno]

( carry propagation TO the most significant bit aka C7) XOR ( Carry out ) is a way to get the signed overflow V as well.
For the new ones: 2s complement and signed share the same meaning.

Here are conditions taken from the ARM specification:
I regrouped them to type:

normal usage:
Z==1 Equal.
Z==0 Not equal.
(.....) True (always jump/execute)

unsigned:
C==1 higher or same
C==0 lower
(C==1) && (Z==0) higher.
(C==0) || (Z==1) lower or same

signed:
N==1 Negative.
N==0 Positive or zero.
V==1 overflow.
V==0 No overflow.
N==V Signed greater than or equal.
N!=V less than.
(Z==0) && (N==V) greater than.
(Z==1) || (N!=V) less than or equal.

On my cpu and on most others, valid sign conditions are nonexistant because it requires you to have atleast a 4 bit operand and the decoder that goes with it.
maybe some considerations:

2 bits: - unsigned only:
00 - always true
01 - C == 1 greater/equal / C==0 lesser than
10 - Z == 0 not equal
11 - Z == 1 equal

3 bits: - unsigned only - <2 operand machines (stack/accumulator)
LZG
L - check for C==0 Lesser than
Z - check for Z==1 Equal
G - check for C==1 && (and) Z==0 Greater than
this means that:
111 - always true
000 - always false / other condition of choice
101 - not equal

3 bits: >= 2 operand machines
Z - check if zero
00Z - always true
01Z - not equal
10Z - unsigned greater/lesser than
11Z - signed greater/lesser than

4bits:
MLZG
M - mode unsigned/signed
disables the L/G check of the other type.

L - check if lesser than
unsigned C==0 / signed N!==V

Z - check if equal
Z==1

G - check if greater than
unsigned C==1 && Z==0 / signed N==V && Z==0

does anyone else have ideas?