09-12-2016, 08:23 PM
(09-12-2016, 10:16 AM)Koyarno Wrote: Some suggestions:
What about a 2 operand IS with a 4 bit opcode? A as source and destination and B only as source.
Register 4 could be a stack to handle the load immidiates and memory operations if you dont want to deal with 2-word instructions.
If you want to start on pipelines, best is to keep to 2 stages. A fetch/decode and Execute so you dont have to deal with forwarding/stack inconsistensies.
It also makes conditional jumps right in line with the conditions from the previous instruction, so no flushing of wrong instructions is needed.
Hope that helps out
That was my plan, 4 bit opcode and 2 operand layout using operations like += and -=. Of course the immediate would use a full word (both operands) so it will probably have a designated register (though it's also GPR). Another idea, I could remove 2 bits off the opcode for the "add immediate" instruction - there will likely be enough extra instruction space to do so.
There won't be any "memory operations" as there won't be any external memory to work upon. Existing ALU operations like add/subtract can be used to move register values around if (but not likely to be) needed.
Thanks for the pipelining advice too. This is my first time so it's going to be fun learning how to implement it.
I'M BAAAAAAACK!