(09-13-2016, 06:22 AM)Nickster258 Wrote: I find your ADDi very interesting.
Definitely tempted to do something similar to this for my next(hell, maybe?) project.
Yeah, variable length opcodes are in a lot of RISC architectures. See page 13 on this pdf (ARM instruction set) for an example. In most of those cases, the opcode is partially replaced with flags that modify the behavior of the operation, but some others use the extra space for more operands.
I'M BAAAAAAACK!