yup, the core of this screen is my 2x2 D-latch design that also allows propogation to the next D-latch below it. Each cell takes 3 inputs: Serial enable, Data in, and Clock.
Serial enable controls a comparator read which takes the upper latch output and lets it go to the lower latch's input.
It's also naturally 2 tick serial, so it would be very easy to interface with loads of stuff.
![[Image: GGJiL18.png]](http://i.imgur.com/GGJiL18.png)
Reading from this screen serially is destructive, but I worked around that by having the data loop back and relatch on that orange global bus.
(If you're wondering why the data and clock inputs are connected, I use an SS of 1 to write a zero and an SS of 2 or more to write a one)
Serial enable controls a comparator read which takes the upper latch output and lets it go to the lower latch's input.
It's also naturally 2 tick serial, so it would be very easy to interface with loads of stuff.
Reading from this screen serially is destructive, but I worked around that by having the data loop back and relatch on that orange global bus.
(If you're wondering why the data and clock inputs are connected, I use an SS of 1 to write a zero and an SS of 2 or more to write a one)