Instruction Set

[LordDecapo]

1. the units are physically separate except for storage, I/O and they do not share the same address space (im talking von neumann ofc).
In the real world they are the dual socket motherboards and they each have their own set of RAM.

Pst, that's multi CPU not Multicore
Your 2 was spot on tho

My idea behind more cores was you can run an os and an other program on the same time, but if i only do one core wich is simpler, i have to multitask, it wil be done by the os, and it is basicaly calling subroutines wich are programs. And i also am going to make my cpu pipelined wich make it much faster. do i need extra instructions for that?
Over all, does someone an other instruction on the empty space, or additions to instructions, pleace reply it. I want to make this ISA as universal as posslible, because i want to use it on every computer i am going to build.

Advice: don't limit yourself to 1 IS, don't be afraid to realize u messed something up and change it or start from scratch in between CPUs. 

Read bottom of reply for stuff on ur OS ideas.

Don't overdo it one step at a time plz

as for pipelining ask me or Lorddecapo, we both know a great deal and no you dont need extra instructions for that. It will give you more headaches though

YES^^ before you jump right into making a multicore pipeline system with an OS... make sure you can make a basic CPU, then one tthat is Pipelined, then learn cache and cache coherency. 
Lastly, get a basic Kernel (lower level name/system of an OS) that works on a single pipelined core well before you think of making a multicore kernel system. There are so many things you haven't gotten to yet that are critical to multicore functionality which have a basis in single core kernel functions I.E. Thread scheduling, memory protection, exception handling etc.

PS. Hi, I'm the LordDecapo that was mentioned. I'm currently working on my 21st CPU architecture using my like 100th IS. And am just now trying to get into kernel/OS development, it's a lot more complex then you may be thinking it is.

Reply to this aasking about Minora if you are interested in my current design and why I'm approaching it the way I am.

https://docs.google.com/spreadsheets/d/1...sp=sharing
here is the link:
Tnx for your suggestions
the ram wil be arranged by the os, program know how much mem. it want, tels it to the os, os tell, you can use everything between this and this address. Also i added a new thing, data transfer, which can move data form address a to b and move it to c, this can be done between the drive and the ram. in the time it is transferring the clock wil be on halt until it is done.
Und everyting in a row
we have one ram which is fully accesable by every program
i think this isa wil be it
we have an os
1 single program running at the time wich wil be stopt by the os
it is made for pipelining but the boubles wil be done in the hardware, than you need less software
we have an cache 8 or 12, two parts on both sides of the alu 3X4  per cell+crtl fuctions
and thank you for your tips

As I mentioned above, learning about thread scheduling, pipelines, and other things like Interrupts and types of intterupts would help you tremendously in these endeavours of yours.

Abstracting a user interface that is even remotely user friendly can be a very tedious task. Involving making many many different sub functions in the kernel to handle the vast amounts of situations tthat can arise dduring normal system operations.