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+---- Thread: Instruction Set (/thread-10324.html)
Instruction Set - Matthijs de bruijn* - 07-16-2016
Hello,
I am making an isa.
My goal is to make it very easy for the computer to decode,
it only contains 16 operations: 8 math 4 branch 3 data 1 control.
But maybe you are thinking, that is not a lot, but wait, if you have only 4 bits for the opcode and 9 for the A, B, C arguments, you left over 3 bits of D arguments so you can have a lot of options in one operations which is very cool!
you need a smal decoder for the instructions
for the instructions i used a lot of the same format, and all extra stuf can be decoded in the specific hardware itself.
this ''/'' means there is an option (load/store
"stack" means ther is an option to use the stack instead of register 7
Here is my isa:
Opcode
Input A
Input B
Extra
Output C
0Addition
ADD
RA
RB
Carry
increment
stack
RC
1Subtraction
SUB
RA
RB
Carry
Decrement
stack
RC
2Multiply
MUL
RA
RB
stack
RC
3Divide
DIV
RA
RB
stack
RC
4Bitwise or
OR
RA
RB
1=invert out
stack
RC
5Bitwise nand
NND
RA
RB
1=invert out
stack
RC
6Bitwise xor
XOR
RA
RB
1=invert out
stack
RC
7Left/Right shift
SFT
RA
Amount shifting
Shift L/shift R
Rotate on/off
stack
RC
Jump if
JMP
RA
Invert
4 bit flag address
4 bit flag address
Offset/Jump
x
Set one if
STO
x
Invert
4 bit flag address
4 bit flag address
Offset/Jump
RC
Monitor flag
MTF
RA
Invert
First 4 flags
4 bit flag address
Offset/Jump
Branch when store to RC
Call
CLL
RA
RB
stack
x
Load constant
CON
1st and 2nd part
8 bit numb
8 bit numb
8 bit numb
RC
Load store IO ports
IOP
RA/RC
RB
Load/store
stack
Internal registers
Load/store reg
LSR
RA/RC
RB
Load/Store
Ram/IO
Stack
0 port+dat
1 port
2 port+latch
3 data+data
Control
CRT
RA
Message to UI
x
0 shutdown
1 exit bios program
2 return from subroutine
3 nop
4 end interrupt
5 halt
6 mode
7 End file
Modes:
0. Normal
1. fpu
2. simd
3. immediate
return form subroutine:
RC return value
On word it looks like beter but maybe you can see what i mean with my isa and you als can download it.
If you have any question or something i can add because there are a lot of empty spaces, tell me. My computer isn't don yet.
(I am dutch so maybe my enlish is not so good)
Mattthijs (MCMatthijs)
RE: Instruction Set - Koyarno - 07-17-2016
Hi mathijs,
Most people use 4/5 bits for opcode and 3 bits for registers
You're not alone there.I mostly use spreadsheets from google docs:
https://docs.google.com/spreadsheets/d/1nn-vKf-SNWhRxzGm9_sCx09_FcwTE-CSYJlil5kGnhQ/edit?usp=sharing
It makes it easier for others to see what it does.
- is it an idea to make the stack refer to a particular register (like 111 = stack) it makes decoding it somewhat easier
- because its a 16 bit IS you could have some more stuff like addimmidiate stuff so you dont have to sacrifice registers for constants
RE: Instruction Set - Matthijs de bruijn* - 07-17-2016
Tnx for you reply,
The idea behind register 7 or stack was that i have 1 more register, but i can make r7 is the stack and make that extra option for imediate values.
I also am going to make a cpu for this thing. But i can'not chose between 8 or 16 bits. 8 bit is faster but 16 bits is enable to have only one calculation per hard disk acces.
Some other people who know some cool extra cool things for my Isa
RE: Instruction Set - Koyarno - 07-17-2016
I would advise not going beyond 8 bits, only if you do floating point stuff. We can mostly work on 8 bit values and when higher is required we use the flags to extend the calculation. Lag as well as size makes it a bit unwieldy. I am not sure about what you mean by the 16 bit storage access though; normally you don't use storage like you do RAM (chunks of data rather).
RE: Instruction Set - Matthijs de bruijn* - 07-17-2016
Here is a spread sheat i made: https://docs.google.com/spreadsheets/d/1YrQRyKM3jy-w2YQJn46C-PnkPU55uEjxiy5ThXXFHwo/edit#gid=0
I mean if you have a hard drive from 2kb you need 11 bits, it is easier to calculate with an 16 bit, but i also can use two instructions for that.
I am going to make more cores, does someone know extra instuctions for multicore processing. Or do i have to implement those things in hardware.
I am going to make it 8 bit.
RE: Instruction Set - Koyarno - 07-17-2016
Do you need that much for a single program or just for giggles? There is a price you pay for asking a single or double byte from a 11 bit address space. Try to look for what speed you want to trade in relation to the address space. I personally use 32 bytes that i keep close and the storage has multiple lanes to it so it can load and store the blocks without waiting a century.
There are multiple things you can do, but that is pretty sophisticated stuff.
As for multicore processing there are two ways really:
1. the units are physically separate except for storage, I/O and they do not share the same address space (im talking von neumann ofc).
In the real world they are the dual socket motherboards and they each have their own set of RAM.
2. the units share the same address space; They both work on different threads; EG small programs that can be run independent of one another.
This does require you to know how to work with caches; A LOT. You've got to work with race conditions and memory hazards.
for MC its not really efficient since doing more stuff = more lag = slower cpu and in the real world the only thing that increases is power draw, not speed. We rather try to improve in other areas like clock speed (pipelining and instruction set effectiveness for example)
RE: Instruction Set - Matthijs de bruijn* - 07-17-2016
My idea behind more cores was you can run an os and an other program on the same time, but if i only do one core wich is simpler, i have to multitask, it wil be done by the os, and it is basicaly calling subroutines wich are programs. And i also am going to make my cpu pipelined wich make it much faster. do i need extra instructions for that?
Over all, does someone an other instruction on the empty space, or additions to instructions, pleace reply it. I want to make this ISA as universal as posslible, because i want to use it on every computer i am going to build.
RE: Instruction Set - Koyarno - 07-17-2016
You didn't give me the public share link though, and i dont use microsoft word < we dont have write access ofcourse to your docs
Basically any cpu with a call stack can handle multiple execution layers, like say an OS/file manager that points to a particular program. So if you return from the program you pop the recent value from the stack and you can continue from that point on. Though do keep in mind that you cannot interrupt the program from outside, it has to terminate on its own. If you do want more flexibility on this you should consider looking up context switching among other things.
Don't overdo it
one step at a time plzas for pipelining ask me or Lorddecapo, we both know a great deal and no you dont need extra instructions for that. It will give you more headaches though
RE: Instruction Set - Matthijs de bruijn* - 07-17-2016
I also am going to aply a cache = )
RE: Instruction Set - Matthijs de bruijn* - 07-18-2016
https://docs.google.com/spreadsheets/d/1YrQRyKM3jy-w2YQJn46C-PnkPU55uEjxiy5ThXXFHwo/edit?usp=sharing
here is the link:
Tnx for your suggestions
the ram wil be arranged by the os, program know how much mem. it want, tels it to the os, os tell, you can use everything between this and this address. Also i added a new thing, data transfer, which can move data form address a to b and move it to c, this can be done between the drive and the ram. in the time it is transferring the clock wil be on halt until it is done.
Und everyting in a row
we have one ram which is fully accesable by every program
i think this isa wil be it
we have an os
1 single program running at the time wich wil be stopt by the os
it is made for pipelining but the boubles wil be done in the hardware, than you need less software
we have an cache 8 or 12, two parts on both sides of the alu 3X4 per cell+crtl fuctions
and thank you for your tips
RE: Instruction Set - Koyarno - 07-18-2016
last question: What kind of instruction memory do you use? i myself got a cache system and tuchi if you want to look up some. I'm on vacation on my laptop so i'm a bit handicapped right now.
Also you can re arrange that immidiate control bit to right after the opcode, It makes the last 8 bits clean for a immidiate.
Operand D seems to be just miscelanious to the opcode.
Oh nevermind i saw the constant opcode, it seems fine really
RE: Instruction Set - MW3_587786 - 07-25-2016
k den
RE: Instruction Set - LordDecapo - 07-28-2016
(07-17-2016, 03:49 PM)Koyarno Wrote: 1. the units are physically separate except for storage, I/O and they do not share the same address space (im talking von neumann ofc).
In the real world they are the dual socket motherboards and they each have their own set of RAM.
Pst, that's multi CPU not Multicore
Your 2 was spot on tho
(07-17-2016, 06:54 PM)Matthijs de bruijn* Wrote: My idea behind more cores was you can run an os and an other program on the same time, but if i only do one core wich is simpler, i have to multitask, it wil be done by the os, and it is basicaly calling subroutines wich are programs. And i also am going to make my cpu pipelined wich make it much faster. do i need extra instructions for that?
Over all, does someone an other instruction on the empty space, or additions to instructions, pleace reply it. I want to make this ISA as universal as posslible, because i want to use it on every computer i am going to build.
Advice: don't limit yourself to 1 IS, don't be afraid to realize u messed something up and change it or start from scratch in between CPUs.
Read bottom of reply for stuff on ur OS ideas.
(07-17-2016, 07:12 PM)Koyarno Wrote: Don't overdo it
as for pipelining ask me or Lorddecapo, we both know a great deal and no you dont need extra instructions for that. It will give you more headaches though
YES^^ before you jump right into making a multicore pipeline system with an OS... make sure you can make a basic CPU, then one tthat is Pipelined, then learn cache and cache coherency.
Lastly, get a basic Kernel (lower level name/system of an OS) that works on a single pipelined core well before you think of making a multicore kernel system. There are so many things you haven't gotten to yet that are critical to multicore functionality which have a basis in single core kernel functions I.E. Thread scheduling, memory protection, exception handling etc.
PS. Hi, I'm the LordDecapo that was mentioned. I'm currently working on my 21st CPU architecture using my like 100th IS. And am just now trying to get into kernel/OS development, it's a lot more complex then you may be thinking it is.
Reply to this aasking about Minora if you are interested in my current design and why I'm approaching it the way I am.
(07-18-2016, 06:14 AM)Matthijs de bruijn* Wrote: https://docs.google.com/spreadsheets/d/1YrQRyKM3jy-w2YQJn46C-PnkPU55uEjxiy5ThXXFHwo/edit?usp=sharing
here is the link:
Tnx for your suggestions
the ram wil be arranged by the os, program know how much mem. it want, tels it to the os, os tell, you can use everything between this and this address. Also i added a new thing, data transfer, which can move data form address a to b and move it to c, this can be done between the drive and the ram. in the time it is transferring the clock wil be on halt until it is done.
Und everyting in a row
we have one ram which is fully accesable by every program
i think this isa wil be it
we have an os
1 single program running at the time wich wil be stopt by the os
it is made for pipelining but the boubles wil be done in the hardware, than you need less software
we have an cache 8 or 12, two parts on both sides of the alu 3X4 per cell+crtl fuctions
and thank you for your tips
As I mentioned above, learning about thread scheduling, pipelines, and other things like Interrupts and types of intterupts would help you tremendously in these endeavours of yours.
Abstracting a user interface that is even remotely user friendly can be a very tedious task. Involving making many many different sub functions in the kernel to handle the vast amounts of situations tthat can arise dduring normal system operations.