03-10-2015, 09:20 PM
(03-10-2015, 07:46 PM)LordDecapo Wrote: have you done variable length instructions before?
You appear to see into my frightened soul !!! This is the aspect of my current build I am most fearful of (variable length instructions: 1 or 2 bytes, and variable execution time: up to 5ish cycles).LordDecapo Wrote:Also, I would suggest getting rid of the bloat inst. In there that you will almost never use. 8 bit opcode can be a bit much to decode each one then encode to the control lines.
5 bit opcode seems to be a good common ground (for MC) between lots of ops and size of system.
8bit opcode CPU in MC would end up being about 50%+ just inst decoding.
Excellent advice, thank you. This one I'm already on... I have stripped down the IS considerably. Thanks for the 5-bit suggestion; it's good to have a ballpark figure.
As for the two approaches to decoding variable length instructions, I think I'm looking at something more like the 1st idea, but I'm hoping I don't need a full "instruction queue": just an InstructionRegister (holds currently executing opcode) and a Data/AddressRegister that is only read into when executing a 2-byte instruction. (Yes, arguably this is a 2-slot queue.) I'll only increment the PC when a value is clocked into one of these two registers. Possibly, I can even re-use the InstructionRegister, so that I don't need the Data/AddressRegister.
The ugly/scary part is having some type of state-machine (inside the computer's execution control logic) that tells it what to do on each cycle for each instruction. It feels like I'm building a computer inside of my computer - but maybe that's necessary so that I can build up layers of abstraction.
Thanks again for taking the time to comment and provide guidance - it is very much appreciated, and probably I will have some questions to ask as I finalise the design.