01-28-2015, 06:30 AM
UPDATE:
picked my final part layout for r13, and will still be able to do 8 tick 4 stage, yet I think I will have to still have a 1 cycle penalty for pointers, which given that a standard Load/Store being a 2 line Opperation, it is kinda a mood point, and doesn't make to much of a difference. Plus it's 3 penalty cycles faster regarding pointers then r12.
I got the ALU, serial In, A serial Out, Reg, and data Stack placed currently, will work on a new RAM design (not serial based this time) to install tomorrow. Then I can get my final Central Data Buss connections done.
If u want to see it, warp IizR then just fly straight, ulll see a bigger dataloop like assembly a little bit out there about the Y height of the r12 CPU.
Well ya,
I'll update this as I get my renovations done. Got a good idea for a self adapting decoder for my multi line inst, I'll post about ut after I make a version for r13
picked my final part layout for r13, and will still be able to do 8 tick 4 stage, yet I think I will have to still have a 1 cycle penalty for pointers, which given that a standard Load/Store being a 2 line Opperation, it is kinda a mood point, and doesn't make to much of a difference. Plus it's 3 penalty cycles faster regarding pointers then r12.
I got the ALU, serial In, A serial Out, Reg, and data Stack placed currently, will work on a new RAM design (not serial based this time) to install tomorrow. Then I can get my final Central Data Buss connections done.
If u want to see it, warp IizR then just fly straight, ulll see a bigger dataloop like assembly a little bit out there about the Y height of the r12 CPU.
Well ya,
I'll update this as I get my renovations done. Got a good idea for a self adapting decoder for my multi line inst, I'll post about ut after I make a version for r13