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IizRr13? - LordDecapo - 01-18-2015

As many of you know, I have been working on a massive computer build on the server (@ warp IizR) complete with 7 stage pipeline, 10tick clock, RAM, FULL hardware support with interrupts, blah blah blah blah. (You almost all probably have heard my shpeel on it before).

So here lies the magical super question of the day, Should I revamp the build layout for the 13th time since this whole big project started, in order to reduce clock speed from 10 to 8 and lower stage count from 7 to about 4-5 stages.
this revamp will also get rid of my only stalling issue (with pointers), and lower my branch mispredict penalty from 4-5 cycles down to 1-2, I will also be able to reduce my Interrupt response time from the 3rd cycle after receiving at best, down to the next cycle after being received.


RE: IizRr13? - Nuuppanaani - 01-18-2015

You need to show a real world example of what your puter is capable of and get in the news :p

RE: IizRr13? - LordDecapo - 01-18-2015

I'm actually getting FPGA, Verilog software, and better computer with my tax return so I can make a IRL example of the architecture xD

RE: IizRr13? - embizone - 01-18-2015

What sort of optimizations will you be implementing to achieve the 8 tick clock?

RE: IizRr13? - LordDecapo - 01-19-2015

@embi, Current queue design I have for the multi line instructions, makes it so it forces me to add 2 extra cycles to all op, even tho there is only 1 op with 3 lines. Current design will optimize for the "most often case" by having the same kinda queue, but it only pushes lines deeper if it gets a multi line op. I will be using that as well as writeback/fwd optimization to reduce my number of stages

As for the clock speed, the Fwd/writeback mods helps that too. By allowing me to fwd not just one inst back, but a 2nd inst back as well.
In the current decoder I ended up realizing, there was only 1 spot in the decoding itself that needed the 10 tick clock, and that was a single branch control line.. which with the new queue setup and orientation of where the PC is. I can shorten that control lines delay.
as well as I have some stuff inside my CO controler, that I thought I would use, but never needed all that extra controlability, (since I changed IS a bunch mid build).

Tl;Dr... I'm moving stuff around, removing redundant logic, and organizing things so bussing delay is more unified. As well as optimizing my decoder a bit more.

RE: IizRr13? - Apocryphan - 01-20-2015

how many comparators did it have and how many are you adding? not enough i bet...

RE: IizRr13? - LordDecapo - 01-22-2015

Sooo many, just so many, the way I run my decoding system, I use a lot of comparator based read locks, as well. Not much logic with them besides this xD

RE: IizRr13? - LordDecapo - 01-22-2015

Oh and votes are 6 to 3, plus the 3 ppl in the group that help me (used to be just Dylan, Voltz, and I.. now we have Tuchi my trial-twin! Tay trial twin! ). All agree that a new system should be made, so yup! Starting it tonight after I get home and actually have a laptop charger xD

RE: IizRr13? - Apocryphan - 01-23-2015

+1 do it

RE: IizRr13? - LordDecapo - 01-28-2015

picked my final part layout for r13, and will still be able to do 8 tick 4 stage, yet I think I will have to still have a 1 cycle penalty for pointers, which given that a standard Load/Store being a 2 line Opperation, it is kinda a mood point, and doesn't make to much of a difference. Plus it's 3 penalty cycles faster regarding pointers then r12.
I got the ALU, serial In, A serial Out, Reg, and data Stack placed currently, will work on a new RAM design (not serial based this time) to install tomorrow. Then I can get my final Central Data Buss connections done.

If u want to see it, warp IizR then just fly straight, ulll see a bigger dataloop like assembly a little bit out there about the Y height of the r12 CPU.

Well ya, Big Grin I'll update this as I get my renovations done. Got a good idea for a self adapting decoder for my multi line inst, I'll post about ut after I make a version for r13